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CY62167EV18LL-55BAXI

P1-P3P4-P6P7-P9P10-P12P13-P13
CY62167EV18 MoBL
®
Document #: 38-05447 Rev. *G Page 4 of 13
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
VFBGA
(6 x 7 x 1mm)
VFBGA
(6 x 8 x 1mm)
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
27.74 55 °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
9.84 16 °C/W
Figure 2. AC Test Loads and Waveforms
Parameters 1.8V Unit
R1 13500 Ω
R2 10800 Ω
R
TH
6000 Ω
V
TH
0.80 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[4]
Max Unit
V
DR
V
CC
for Data Retention 1.0 V
I
CCDR
[9]
Data Retention Current V
CC
= 1.0V, CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
10 μA
t
CDR
[10]
Chip Deselect to Data
Retention Time
0ns
t
R
[11]
Operation Recovery Time t
RC
ns
Figure 3. Data Retention Waveform
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V
CC
ramp from V
DR
to V
CC
(min) > 100 μs or stable at V
CC
(min) > 100 μs.
12. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC
(min)
V
CC
(min)
t
CDR
V
DR
>
1.0 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE.BLE
CE
2
or
[12]
[+] Feedback
CY62167EV18 MoBL
®
Document #: 38-05447 Rev. *G Page 5 of 13
Switching Characteristics
Over the Operating Range
[13, 14]
Parameter Description
55 ns
Unit
Min Max
Read Cycle
t
RC
Read Cycle Time 55 ns
t
AA
Address to Data Valid 55 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 55 ns
t
DOE
OE LOW to Data Valid 25 ns
t
LZOE
OE LOW to Low-Z
[15]
5ns
t
HZOE
OE HIGH to High-Z
[15, 16]
18 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low-Z
[15]
10 ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High-Z
[15, 16]
18 ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up 0 ns
t
PD
CE
1
HIGH and CE
2
LOW to Power Down 55 ns
t
DBE
BLE/BHE LOW to Data Valid 55 ns
t
LZBE
BLE/BHE LOW to Low-Z
[15]
10 ns
t
HZBE
BLE/BHE HIGH to High-Z
[15, 16]
18 ns
Write Cycle
[17]
t
WC
Write Cycle Time 55 ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End 40 ns
t
AW
Address Setup to Write End 40 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Setup to Write Start 0 ns
t
PWE
WE Pulse Width 40 ns
t
BW
BLE/BHE LOW to Write End 40 ns
t
SD
Data Setup to Write End 25 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High-Z
[15, 16]
20 ns
t
LZWE
WE HIGH to Low-Z
[15]
10 ns
Notes
13. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in AC Test Loads and Waveforms on page 4.
14. AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
16. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the output enters a high impedance state.
17. The internal memory write time is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback
CY62167EV18 MoBL
®
Document #: 38-05447 Rev. *G Page 6 of 13
Switching Waveforms
Figure 4 shows address transition controlled read cycle waveforms.
[18, 19]
Figure 4. Read Cycle No. 1
Figure 5 shows OE
controlled read cycle waveforms.
[19, 20]
Figure 5. Read Cycle No. 2
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
t
RC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
PD
t
HZBE
t
LZBE
t
HZCE
t
DBE
OE
CE
1
ADDRESS
CE
2
BHE/BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH
I
CC
I
SB
IMPEDANCE
Notes
18. The device is continuously selected. OE
, CE
1
= V
IL
, BHE, BLE or both = V
IL
, and CE
2
= V
IH
.
19. WE
is HIGH for read cycle.
20. Address valid before or similar to CE
1
, BHE, BLE transition LOW and CE
2
transition HIGH.
[+] Feedback
P1-P3P4-P6P7-P9P10-P12P13-P13

CY62167EV18LL-55BAXI

Mfr. #:
Buy CY62167EV18LL-55BAXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 16Mbit SRAM 55ns 1.8V CMOS
Lifecycle:
New from this manufacturer.
Delivery:
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