MT89L80 Data Sheet
11
Zarlink Semiconductor Inc.
Figure 10 - Clock Timing
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
AC Electrical Characteristics
†
- Serial Streams (Figures 11, 12 and 13)
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1
O
U
T
P
U
T
S
STo0/7 Delay - Active to High Z t
SAZ
555nsR
L
=1 KΩ*, C
L
=150 pF
2 STo0/7 Delay - High Z to Active t
SZA
555nsC
L
=150 pF
3 STo0/7 Delay - Active to Active t
SAA
555nsC
L
=150 pF
4 Output Driver Enable Delay t
OED
50 ns R
L
=1 KΩ*, C
L
=150 pF
5 External Control Delay t
XCD
55 ns C
L
=150 pF
6
I
N
Serial Input Setup Time t
SIS
20 ns
7 Serial Input Hold Time t
SIH
20 ns
t
CLK
t
CTT
t
CH
t
CHL
t
CTT
t
FPH
t
FPS
t
FPH
t
FPS
t
FPW
t
CL
C4i
F0i
V
HM
V
LM
V
HM
V
LM
