ADV7612 Data Sheet
Rev. E | Page 6 of 20
Timing Diagrams
SD
A
SCL
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
9308-003
Figure 3. I
2
C Timing
t
9
LLC
t
11
t
12
t
10
P0 TO P23, HS,
VS/FIELD/ALSB, DE
9308-004
Figure 4. Pixel Port and Control SDR Output Timing
SCLK
LRCLK
I
2
S
LEFT-JUSTIFIED
MODE
MSB MSB – 1
t
15
t
16
t
17
t
19
t
20
t
18
MSB
MSB – 1
LSBMSB
t
19
t
20
t
19
t
20
NOTES
1. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.
2. I
2
S SIGNALS ARE ACCESSIBLE VIA THE AP1 TO AP4 PINS.
I
2
S
RIGHT-JUSTIFIED
MODE
I
2
S
I
2
S MODE
09308-005
Figure 5. I
2
S Timing
Data Sheet ADV7612
Rev. E | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
DVDD to GND 2.2 V
PVDD to GND 2.2 V
DVDDIO to GND 4.0 V
CVDD to GND 2.2 V
TVDD to GND 4.0 V
Digital Inputs Voltage to GND GND 0.3 V to DVDDIO + 0.3 V
5 V Tolerant Digital Inputs to
GND
1
5.3 V
Digital Outputs Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V
XTALP, XTALN 0.3 V to PVDD + 0.3 V
SCL/SDA Data Pins to DVDDIO
DVDDIO 0.3 V to DVDDIO +
3.6 V
Maximum Junction
Temperature (T
J MAX
)
125°C
Storage Temperature Range −60°C to +150°C
Infrared Reflow Soldering (20 sec) 260°C
1
The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,
DDCA_SDA, DDCB_SCL, and DDCB_SDA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the ADV7612, the
user is advised to turn off the unused sections of the part.
Due to the printed circuit board (PCB) metal variation and,
therefore, variation in PCB heat conductivity, the value of θ
JA
may differ for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the θ
JA
value.
The maximum junction temperature (T
J
MAX
) of 125°C must not be
exceeded. The following equation calculates the junction tempera-
ture using the measured package surface temperature and applies
only when no heat sink is used on the device under test (DUT):
( )
TOTALJT
S
J
WΨTT ×+=
where:
T
S
is the package surface temperature (°C).
Ψ
JT
= 0.3°C/W for the 100-lead LQFP_EP.
W
TOTAL
= ((PVDD × I
PVDD
) + (0.05 × TVDD × I
TVDD
) + (CVDD ×
I
CVDD
) + (DVDD × I
DVDD
) + (DVDDIO × I
DVDDIO
))
where 0.05 is 5% of the TVDD power that is dissipated on the
part itself.
ESD CAUTION
ADV7612 Data Sheet
Rev. E | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
26
27
28
29
30
31
32
33
34
35
36
37
38
39
2
3
4
7
6
5
1
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
74
73
72
69
70
71
75
68
67
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
65
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
ADV7612
TOP VIEW
(Not to Scale)
AP1
AP0
VS/FIELD/ALSB
HS
DE
DVDDIO
P0
P1
P2
P3
P4
P5
P6
DVDD
P7
P8
P9
P10
P11
P12
P13
DVDDIO
P14
P15
P16
CVDD
RXA_C–
RXA_C+
TVDD
RXA_0–
RXA_0+
TVDD
RXA_1–
RXA_1+
TVDD
RXA_2–
RXA_2+
CVDD
RXB_C–
RXB_C+
TVDD
RXB_0–
RXB_0+
TVDD
RXB_1–
RXB_1+
TVDD
RXB_2–
RXB_2+
CVDD
HPA_A/INT2
RXA_5V
DDCA_SDA
DDCA_SCL
HPA_B
RXB_5V
DDCB_SDA
DDCB_SCL
CEC
DVDD
XTALN
XTALP
PVDD
CS
RESET
INT1
SDA
SCL
DVDD
MCLK/INT2
AP5
SCLK/INT2
AP4
AP3
AP2
NC
P35
P34
DVDDIO
P33
P32
P31
P30
P29
P28
P27
DVDDIO
P26
P25
P24
DVDD
LLC
P23
P22
P21
P20
P19
P18
P17
NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. CONNECT EXPOSED PAD (PIN0) TO GROUND (BOTTOM).
09308-008
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Type Description
0 GND Ground Ground.
1 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
2
RXA_C
HDMI input
Digital Input Clock Complement of Port A in the HDMI Interface.
3 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface.
4 TVDD Power Terminator Supply Voltage (3.3 V).
5 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface.
6
RXA_0+
HDMI input
Digital Input Channel 0 True of Port A in the HDMI Interface.
7 TVDD Power Terminator Supply Voltage (3.3 V).
8 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface.
9 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.
10 TVDD Power Terminator Supply Voltage (3.3 V).
11 RXA_2 HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
12
RXA_2+
HDMI input
Digital Input Channel 2 True of Port A in the HDMI Interface.
13 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
14
RXB_C
HDMI input
Digital Input Clock Complement of Port B in the HDMI Interface.

EVAL-ADV7612EB2Z

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video IC Development Tools EVAL-ADV7612
Lifecycle:
New from this manufacturer.
Delivery:
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