December 1990 2
Philips Semiconductors Product specification
Dual 4-bit serial-in/parallel-out shift
register
74HC/HCT4015
FEATURES
• Output capability: standard
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4015 are high-speed Si-gate CMOS
devices and are pin compatible with the “4015” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4015 are dual edge-triggered 4-bit static
shift registers (serial-to-parallel converters). Each shift
register has a serial data input (1D and 2D), a clock input
(1CP and 2CP), four fully buffered parallel outputs (1Q
0
to
1Q
3
and 2Q
0
to 2Q
3
) and an overriding asynchronous
master reset (1MR and 2MR). Information present on nD
is shifted to the first register position, and all data in the
register is shifted one position to the right on the
LOW-to-HIGH transition of nCP.
A HIGH on nMR clears the register and forces nQ
0
to nQ
3
to LOW, independent of nCP and nD.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nCP to nQ
n
C
L
= 15 pF; V
CC
=5 V1618ns
f
max
maximum clock frequency 110 74 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per register notes 1 and 2 35 40 pF
