OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCP1015AP065G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
NCP1015
http://onsemi.com
7
APPLICATION INFORMATION
Introduction
The NCP1015 offers a complete current−mode control
solution (actually an enhanced NCP1200 controller section)
together with a high−voltage power MOSFET in a
monolithic structure. The component integrates everything
needed to build a rugged and low−cost Switch−Mode Power
Supply (SMPS) featuring low standby power. The quick
selection table details the differences in operating
frequency.
• No need for an auxiliary winding: ON Semiconductor
Very High Voltage Integrated Circuit technology lets
you supply the IC directly from the high−voltage dc
rail. We call it Dynamic Self−Supply (DSS). This
solution simplifies the transformer design and ensures a
better control of the SMPS in difficult output
conditions, e.g. constant current operations. However,
for improved standby performance, an auxiliary
winding can be connected to the V
CC
pin to disable the
DSS operation.
• Short−circuit protection: by permanently monitoring
the feedback line activity, the IC is able to detect the
presence short−circuit, immediately reducing the output
power for a total system protection. Once the short has
disappeared, the controller resumes and goes back to
normal operation.
• Low standby−power: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less
efficient when the output power demand diminishes. By
skipping un−needed switching cycles, the NCP1015
drastically reduces the power wasted during light load
conditions. An auxiliary winding can further help
decreasing the standby power to extremely low levels
by invalidating the DSS operation. Typical
measurements show results below 80 mW @ 230 Vac
for a typical 7 W universal power supply.
• No acoustic noise while operating: Instead of skipping
cycles at high peak currents, the NCP1015 waits until
the peak current demand falls below a fixed 0.25 of the
maximum limit. As a result, cycle skipping can take
place without having a singing transformer. You can
thus select cheap magnetic components free of noise
problems.
• SPICE model: a dedicated model to run transient
cycle−by−cycle simulations is available but also an
averaged version to help you closing the loop.
Ready−to−use templates can be downloaded in
OrCAD’s PSpice, and INTUSOFT’s IsSpice4 from ON
Semiconductor web site, NCP1015 related section.
Dynamic Self−Supply
When the power supply is first powered from the mains
outlet, the internal current source (typically 8 mA) is biased
and charges up the V
CC
capacitor from the drain pin. Once
the voltage on this V
CC
capacitor reaches the V
CC(off)
level
(typically 8.5 V), the current source turns off and pulses are
delivered by the output stage: the circuit is awake and
activates the power MOSFET. Figure 12 details the internal
circuitry:
Figure 12. The Current Source Regulates V
CC
by Introducing a Ripple
Vref OFF = 8.5 V
Vref ON = 7.5 V
Vref
Latch
= 4.7 V
-
+
Internal Supply
+
Vref
V
CC(off)
+200 mV
(8.7 V Typ.)
V
CC
+
CV
CC
Startup Source
Drain
Being loaded by the circuit consumption, the voltage on
the V
CC
capacitor goes down. When the DSS controller
detects that V
CC
has reached 7.5 V (V
CC(on)
), it activates the
internal current source to bring V
CC
toward 8.5 V and stops
again: a cycle takes place whose low frequency depends on
the V
CC
capacitor and the IC consumption. A 1 V ripple
takes place on the V
CC
pin whose average value equals
(V
CC(off)
+ V
CC(on)
) / 2. Figure 13 shows a typical operation
of the DSS.
NCP1015
http://onsemi.com
8
0
2.00
4.00
6.00
8.00
Startup period
Vcc
8.5V
7.5V
Device
internally
pulses
Figure 13. The Charge/Discharge Cycle over a 10 mF V
CC
Capacitor
As one can see, the V
CC
capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
reached before V
CC
crosses 7.5 V (otherwise the part enters
the fault condition mode). If we know that DV = 1 V and
ICC1 is 1.2 mA (for instance we selected a 11 W device
switching at 65 kHz), then the V
CC
capacitor can be
calculated using:
C w
ICC1 @ t
startup
DV
(eq. 1)
Let’s suppose that the SMPS needs 10 ms to startup, then
we will calculate C to offer a 15 ms period. As a result, C
should be greater than 18 mF thus the selection of a 33 mF /
16 V capacitor is appropriate.
Short Circuit Protection
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (V
out
is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
for the presence of the error flag every time V
CC
crosses
V
CC(on)
. If the error flag is low (peak limit not active) then
the IC works normally. If the error signal is active, then the
NCP1015 immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: V
CC
drops toward ground until it reaches
the so−called latch−off level, where the current source
activates again to attempt a new re−start. If the error has
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch−off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short−circuit. Figure 14
presents the corresponding diagram:
Figure 14. Simplified NCP1015 Short−Circuit
Detection Circuitry
−
+
4 V
FB
Division
Max
Ip
Flag
V
CC
V
CC(on)
To
Latch
Reset
Current Sense
Information
Clamp
Active?
The protection burst duty−cycle can easily be computed
through the various timing events as portrayed by Figure 15:
NCP1015
http://onsemi.com
9
Figure 15. NCP1015 Facing a Fault Condition (V
in
= 150 Vdc)
Tstart
Tsw
TLatch
1 V Ripple
Latch−off
Level
The rising slope from the latch−off level up to 8.5 V is
expressed by:
P
DSS
+ V
in
@ ICC1
t
start
+
DV1 @ C
IC1
The time during which the IC actually pulses is given by:
t
sw
+
DV2 @ C
ICC1
Finally, the latch−off time can be derived using the same
formula topology:
t
latch
+
DV3 @ C
ICC2
From these three definitions, the burst duty−cycle D can
be computed:
D +
t
sw
t
start
) t
sw
) t
latch
(eq. 2)
D +
DV2
ICC1 @
ǒ
DV2
ICC1
)
DV1
IC1
)
DV3
ICC2
Ǔ
(eq. 3)
Feeding the equation with values extracted from the
parameter section gives a typical duty−cycle D of 13%,
precluding any lethal thermal runaway while in a fault
condition.
DSS Internal Dissipation
The Dynamic Self−Supplied pulls the energy out from the
drain pin. In the Flyback−based converters, this drain level
can easily go above 600 V peak and thus increase the stress
on the DSS startup source. However, the drain voltage
evolves with time and its period is small compared to that of
the DSS. As a result, the averaged dissipation, excluding
capacitive losses, can be derived by:
P
DSS
+ ICC1 @t V
DS(t)
u
(eq. 4)
Figure 16 shows a typical drain−ground wave−shape
where leakage effects have been removed:
Figure 16. A Typical Drain−ground Waveshape
where Leakage Effects are Not Accounted for
Vds(t)
Vin
Vr
toff
dt
ton
t
Tsw
By looking at Figure 16 the average result can easily be
derived by additive square area calculation:
t V
DS(t)
u+ V
in
@ (1 * D) ) V
r
@
t
off
t
sw
(eq. 5)
By developing Equation 5 we obtain:
t V
DS(t)
u+ V
in
* V
in
@
t
on
t
sw
) V
r
@
t
off
t
sw
(eq. 6)
t
off
can be expressed by:
t
off
+ I
p
@
L
p
V
r
(eq. 7)
t
on
can be evaluated by:
t
on
+ I
p
@
L
p
V
in
(eq. 8)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

NCP1015AP065G

Mfr. #:
Buy NCP1015AP065G
Manufacturer:
ON Semiconductor
Description:
AC/DC Converters SELF-SUPPLIED MONOLITHIC SWITCHER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet