MC74LVX74MEL

© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 5
1 Publication Order Number:
MC74LVX74/D
MC74LVX74
Dual D-Type Flip-Flop
with Set and Clear
With 5.0 V−Tolerant Inputs
The MC74LVX74 is an advanced high speed CMOS D−type
flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the
interface of 5.0 V systems to 3.0 V systems.
The signal level applied to the D input is transferred to O output
during the positive going transition of the Clock pulse.
Clear (CD
) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
Features
High Speed: f
max
= 145 MHz (Typ) at V
CC
= 3.3 V
Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: V
OLP
= 0.5 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
O1
SD1
Q
4
5
D1 D
2
CP1 CP
3
CD1
1
O1
Q
6
SD
CD
O2
SD2
Q
10
9
D2 D
12
CP2 CP
11
CD2
13
O2
Q
8
SD
CD
See detailed ordering and shipping information in the packag
e
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
MARKING DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
SOIC−14 NB
D SUFFIX
CASE 751A
LVX74 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
W, WW = Work Week
G or G = Pb−Free Package
LVX74G
AWLYWW
1
14
LVX
74
ALYW G
G
1
14
(Note: Microdot may be in either location)
PIN NAMES
Function
Clock Pulse Inputs
Data Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
Pins
CP1, CP2
D1, D2
CD1
, CD2
SD1, SD2
On, On
TSSOP−14SOIC−14 NB
PIN ASSIGNMENT
14−Lead (Top View)
1314 12 11 10 9 8
21 34567
V
CC
CD2 D2 CP2 SD2 O2 O2
CD1 D1 CP1 SD1 O1 O1 GND
MC74LVX74
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2
INPUTS
OUTPUTS
SDn CDn CPn Dn On On OPERATING MODE
L
H
H
L
X
X
X
X
H
L
L
H
Asynchronous Set
Asynchronous Clear
L L X X H H Undetermined
H
H
H
H
h
l
H
L
L
H
Load and Read Register
H H X NC NC Hold
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; L = Low Voltage Level; l = Low Voltage
Level One Setup Time Prior to the Low−to−High Clock Transition; NC = No Change; X = High or Low Voltage Level or Transitions are Acceptable;
= Low−to−High Transition;
= Not a Low−to−High Transition; For I
CC
Reasons DO NOT FLOAT Inputs
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage –0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to +7.0 V
V
out
DC Output Voltage –0.5 to V
CC
+0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation 180 mW
T
stg
Storage Temperature –65 to +150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 3.6 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature, All Package Types −40 +85
_C
Dt/DV
Input Rise and Fall Time 0 100 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= − 40 to 85°C
Unit
Min Typ Max Min Max
V
IH
High−Level Input Voltage 2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
IL
Low−Level Input Voltage 2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
OH
High−Level Output Voltage
(V
in
= V
IH
or V
IL
)
I
OH
= −50mA
I
OH
= −50mA
I
OH
= −4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
V
V
OL
Low−Level Output Voltage
(V
in
= V
IH
or V
IL
)
I
OL
= 50mA
I
OL
= 50mA
I
OL
= 4mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
V
I
in
Input Leakage Current V
in
= 5.5V or GND 3.6 ±0.1 ±1.0
mA
I
CC
Quiescent Supply Current V
in
= V
CC
or GND 3.6 2.0 20.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
MC74LVX74
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3
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= −40 to 85°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Propagation Delay
CP to O or O
V
CC
= 2.7V C
L
= 15pF
C
L
= 50pF
7.3
9.8
15.0
18.5
1.0
1.0
18.5
22.0
ns
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
5.7
8.2
9.7
13.2
1.0
1.0
11.5
15.0
t
PLH
,
t
PHL
Propagation Delay
SD
or CD to O or O
V
CC
= 2.7V C
L
= 15pF
C
L
= 50pF
8.4
10.9
15.6
19.1
1.0
1.0
18.5
22.0
ns
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
6.6
9.1
10.1
13.6
1.0
1.0
12.0
15.5
f
max
Maximum Clock Frequency
(50% Duty Cycle)
V
CC
= 2.7V C
L
= 15pF
C
L
= 50pF
55
45
135
60
50
40
MHz
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
95
60
145
85
80
50
t
OSHL
t
OSLH
Output−to−Output Skew
(Note 1)
V
CC
= 2.7V C
L
= 50pF
V
CC
= 3.3 ±0.3V C
L
= 50pF
1.5
1.5
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
TIMING REQUIREMENTS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
T
A
= 25_C T
A
= −40 to 85_C
t
w
Minimum Pulse Width, CP 2.7V
3.3V ±0.3
8.5
6.0
10.0
7.0
ns
t
w
Minimum Pulse Width, CD or SD 2.7V
3.3V ±0.3
8.5
6.0
10.0
7.0
ns
t
su
Minimum Setup Time, D to CP 2.7V
3.3V ±0.3
8.0
5.5
9.5
6.5
ns
t
h
Minimum Hold Time, D to CP 2.7V
3.3V ±0.3
0.5
0.5
0.5
0.5
ns
t
rec
Minimum Recovery Time, SD or CD to CP 2.7V
3.3V ±0.3
6.5
5.0
7.5
5.0
ns
CAPACITIVE CHARACTERISTICS
Symbo
l
Parameter
T
A
= 25°C T
A
= −40 to 85°C
Unit
Min Typ Max Min Max
Cin Input Capacitance 4 10 10 pF
C
PD
Power Dissipation Capacitance (Note 2) 25 pF
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/2 (per flip−flop). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 3.3V, Measured in SOIC Package)
Symbo
l
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.5 V
V
OLV
Quiet Output Minimum Dynamic V
OL
−0.3 −0.5 V
V
IHD
Minimum High Level Dynamic Input Voltage 2.0 V
V
ILD
Maximum Low Level Dynamic Input Voltage 0.8 V

MC74LVX74MEL

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-3.6V CMOS Dual
Lifecycle:
New from this manufacturer.
Delivery:
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