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MPC9331AC

P1-P3P4-P6P7-P9P10-P12P13-P13
MPC9331 REVISION 7 March 11, 2016 4 ©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet 3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
Table 2. Function Table
Control Default 0 1
REF_SEL 0 PCLK is the PLL reference clock CCLK is the PLL reference clock
FB_SEL 1 Internal PLL feedback of 8. f
VCO
= 8 * f
ref
External feedback. Zero-delay operation
enabled for CCLK or PCLK as reference
clock
PLL_EN 1 Test mode with PLL disabled. The reference clock is
substituted for the internal VCO output. MPC9331 is fully static
and no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
Normal operation mode with PLL enabled.
PWR_DN 1 VCO 1 (High output frequency range) VCO 2 (Low output frequency range)
FSELA 0 Output divider 2 Output divider 4
FSELB 0 Output divider 2 Output divider 4
FSELC 0 Output divider 4 Output divider 6
OE/MR 1 Outputs disabled (high-impedance state) and reset of the
device. During reset in external feedback configuration, the
PLL feedback loop is open. The VCO is tied to its lowest
frequency. The MPC9331 requires reset after any loss of PLL
lock. Loss of PLL lock may occur when the external feedback
path is interrupted. The length of the reset pulse should be
greater than one reference clock cycle (CCLK or PCLK). Reset
does not affect PLL lock in internal feedback configuration.
Outputs enabled (active)
CLK_STOP[0:1] 11 See Table 3
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 8 through Table 10 for supported frequency ranges and output to input frequency ratios.
MPC9331 REVISION 7 March 11, 2016 5 ©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet 3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table
(1)
1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1].
CLK_STOP0 CLK_STOP1 QA[0:1] QB[0:1] QC[0:1]
0 0 Active Stopped in logic L state Stopped in logic L state
0 1 Active Stopped in logic L state Active
1 0 Stopped in logic L state Stopped in logic L state Active
1 1 Active Active Active
Table 4. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
2 V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 2000 V
LU Latch-Up Immunity 200 mA
C
PD
Power Dissipation Capacitance 10 pF Per output
C
IN
Input Capacitance 4.0 pF Inputs
Table 5. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit
V
CC
Supply Voltage –0.3 3.9 V
V
IN
DC Input Voltage –0.3 V
CC
+ 0.3 V
V
OUT
DC Output Voltage –0.3 V
CC
+ 0.3 V
I
IN
DC Input Current 20 mA
I
OUT
DC Output Current 50 mA
T
S
Storage Temperature –65 125 °C
Table 6. DC Characteristics (V
CC
= 3.3 V 5%, T
A
= 0°C to 70°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input high voltage 2.0 V
CC
+ 0.3 V
LVCMOS
V
IL
Input low voltage 0.8 V
LVCMOS
V
PP
Peak-to-peak input voltagePCLK, PCLK 250 mV
LVPECL
V
CMR
(1)
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(DC) specification.
Common Mode RangePCLK, PCLK 1.0 V
CC
– 0.6 V
LVPECL
V
OH
Output High Voltage 2.4 V
I
OH
= –24 mA
(2)
2. The MPC9331 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
V
OL
Output Low Voltage 0.55
0.30
V
V
I
OL
= 24 mA
I
OL
= 12 mA
Z
OUT
Output impedance 14 – 17 W
I
IN
Input Current
(3)
3. Inputs have pull-down or pull-up resistors affecting the input current.
200 A
V
IN
= V
CC
or GND
I
CC_PLL
Maximum PLL Supply Current 8.0 12 mA
V
CC_PLL
Pin
I
CCQ
Maximum Quiescent Supply Current
(4)
4. OE/MR=0 (outputs in high-impedance state).
26 mA
All V
CC
Pins
MPC9331 REVISION 7 March 11, 2016 6 ©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet 3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
Table 7. Characteristics (V
CC
= 3.3V 5%, T
A
= 0°C to 70°C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
REF
Input reference frequency 2 feedback
PLL mode, external feedback 4 feedback
6 feedback
8 feedback
12 feedback
PLL mode, internal feedback (8 feedback)
Input reference frequency in PLL bypass mode
(2)
2. In bypass mode, the MPC9331 divides the input reference clock.
100.0
50.0
33.3
25.0
16.67
25.0
240.0
120.0
80.0
60.0
40.0
60.0
240
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
f
VCO
VCO lock frequency range
(3)
3. The input frequency f
REF
must match the VCO frequency range divided by the feedback divider ratio FB: f
REF
= f
VCO
FB.
200 480 MHz
f
MAX
Output Frequency 2 output
4 output
6 output
8 output
12 output
100.0
50.0
33.3
25.0
16.67
240.0
120.0
80.0
60.0
40.0
MHz
MHz
MHz
MHz
MHz
PLL locked
V
PP
Peak-to-peak input voltage PCLK, PCLK 400 1000 mV LVPECL
V
CMR
(4)
4. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts static phase offset t
()
.
Common Mode Range PCLK, PCLK 1.2 V
CC
– 0.9 V LVPECL
t
PW,MIN
Input Reference Pulse Width
(5)
5. Calculation of reference duty cycle limits: DC
REF,MIN
= t
PW,MIN
f
REF
100% and DC
REF,MAX
= 100% – DC
REF,MIN
.
2.0 ns
t
R
, t
F
CCLK Input Rise/Fall Time
(6)
6. The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
()
, t
PW,MIN
, DC and f
MAX
can only
be guaranteed if t
R
, t
F
are within the specified range.
1.0 ns 0.8 to 2.0 V
t
()
Propagation Delay CCLK to FB_IN
(7)
(static phase offset) PCLK to FB_IN
(7)
CCLK or PCLK to FB_IN
(8)
7. Data valid for f
REF
= 50 MHz and a PLL feedback of 8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1).
8. Data valid for 16.67 MHz < f
REF
< 100 MHz and any feedback divider. t
sk(O)
[s] = t
sk(O)
[] (f
REF
360).
–250
–180
–3.0
–130
–30
–50
+120
+3.0
ps
ps
°
FB_SEL = 1 and
PLL locked
t
sk(O)
Output-to-output Skew 150 ps
DC
Output duty cycle
(9)
9. Output duty cycle is DC = (0.5 500 ps f
OUT
) 100%. (e.g. the DC range at f
OUT
= 100 MHz is 45% < DC < 55%).
(T2)–500 T2 (T2)+500 ps
t
R
, t
F
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V
t
PLZ, HZ
Output Disable Time 8.0 ns
t
PZL, LZ
Output Enable Time 10 ns
t
JIT(CC)
Cycle-to-cycle jitter
(10)
10. All outputs in 4 divider configuration.
200 ps
t
JIT(PER)
Period Jitter 125 ps
t
JIT()
I/O Phase Jitter RMS (1 ) 25 ps
BW
PLL closed loop bandwidth
(11)
4 feedback
PLL mode, external feedback 6 feedback
8 feedback
12 feedback
11. –3 dB point of PLL transfer characteristics.
2.0–8.0
1.2–4.0
1.0–3.0
0.7–2.0
MHz
MHz
MHz
MHz
t
LOCK
Maximum PLL Lock Time 10 ms
P1-P3P4-P6P7-P9P10-P12P13-P13

MPC9331AC

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Manufacturer:
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Description:
Clock Generators & Support Products 3.3V 200MHz Clock Generator
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