AD7705BRZ-REEL7 Datasheet AD7705BRUZ, AD7705BNZ, AD7705BRZ-REEL | P22-P24

AD7705/AD7706

Rev. C | Page 22 of 44

ANALOG INPUT

Ranges

The AD7705 contains two differential analog input pairs,

AIN1(+)/AIN1(−) and AIN2(+)/AIN2(−). These input pairs

provide programmable-gain, differential input channels that can

handle either unipolar or bipolar input signals. It should be noted

that the bipolar input signals are referenced to the respective

AIN(−) input of each input pair. The AD7706 contains three

pseudo differential analog input pairs, AIN1, AIN2, and AIN3,

which are referenced to the COMMON input.

In unbuffered mode, the common-mode range of the input is

from GND to V

, provided that the absolute value of the analog

input voltage lies between GND − 100 mV and V

+ 30 mV.

Therefore, in unbuffered mode, the part can handle both unipolar

and bipolar input ranges for all gains. The AD7705 can tolerate

absolute analog input voltages down to GND − 200 mV, but the

leakage current increases at high temperatures. In buffered mode,

the analog inputs can handle much larger source impedances,

but the absolute input voltage range is restricted to between

GND + 50 mV and V

− 1.5 V, which also restricts the common-

mode range. Therefore, in buffered mode, there are some

restrictions on the allowable gains for bipolar input ranges. Care

must be taken in setting up the common-mode voltage and

input voltage ranges so that the above limits are not exceeded;

otherwise, there is a degradation in linearity performance.

In unbuffered mode, the analog inputs look directly into the

7 pF input sampling capacitor, C

SAMP

. The dc input leakage

current in this unbuffered mode is 1 nA maximum. As a result,

the analog inputs see a dynamic load that is switched at the

input sample rate (see

Figure 14). This sample rate depends on

master clock frequency and selected gain. C

SAMP

is charged to

AIN(+) and discharged to AIN(−) every input sample cycle.

The effective on resistance of the switch, R

, is typically 7 kΩ.

SAMP

must be charged through R

and any external source

impedances every input sample cycle. Therefore, in unbuffered

mode, source impedances mean a longer charge time for C

SAMP

which might result in gain errors on the parts.

Table 22 shows

the allowable external resistance-capacitance values for unbuffered

mode, such that no gain error to the 16-bit level is introduced in

the part. Note that these capacitances are total capacitances on

the analog input—external capacitance plus 10 pF capacitance

from the pins and lead frame of the devices.

AIN(+)

AIN(–)

SWITCHING FREQUENCY DEPENDS ON

CLKIN

AND SELECTED GAIN

(7kΩ TYP)

SAMP

(7pF)

HIGH

IMPEDANCE

>1G

BIAS

01166-014

Figure 14. Unbuffered Analog Input Structure

Table 22. External Resistance-Capacitance Combination for

Unbuffered Mode (Without 16-Bit Gain Error)

External Capacitance (pF)

Gain 10 50 100 500 1000 5000

1 152 kΩ 53.9 kΩ 31.4 kΩ 8.4 kΩ 4.76 kΩ 1.36 kΩ

2 75.1 kΩ 26.6 kΩ 15.4 kΩ 4.14 kΩ 2.36 kΩ 670 Ω

4 34.2 kΩ 12.77 kΩ 7.3 kΩ 1.95 kΩ 1.15 kΩ 320 Ω

8 to 128 16.7 kΩ 5.95 kΩ 3.46 kΩ 924 Ω 526 Ω 150 Ω

In buffered mode, the analog inputs look into the high impedance

inputs stage of the on-chip buffer amplifier. C

SAMP

is charged via

this buffer amplifier such that source impedances do not affect

the charging of C

SAMP

. This buffer amplifier has an offset leakage

current of 1 nA. In this buffered mode, large source impedances

result in a small dc offset voltage developed across the source

impedance, but not in a gain error.

Sample Rate

The modulator sample frequency for the AD7705/AD7706

remains at f

CLKIN

/128 (19.2 kHz @ f

CLKIN

= 2.4576 MHz), regardless

of the selected gain. However, gains greater than 1 are achieved

by a combination of multiple input samples per modulator cycle

and a scaling of the ratio of reference capacitor to input capacitor.

As a result of the multiple sampling, the input sample rate of

these devices varies with the selected gain (see

Table 23). In

buffered mode, the input is buffered before the input sampling

capacitor. In unbuffered mode, where the analog input looks

directly into the sampling capacitor, the effective input impedance

is 1/C

SAMP

× f

, where C

SAMP

is the input sampling capacitance

and f

is the input sample rate.

Table 23. Input Sampling Frequency vs. Gain

Gain Input Sampling Frequency (f

)

1 f

CLKIN

/64 (38.4 kHz @ f

CLKIN

= 2.4576 MHz)

2 2 × f

CLKIN

/64 (76.8 kHz @ f

CLKIN

= 2.4576 MHz)

4 4 × f

CLKIN

/64 (76.8 kHz @ f

CLKIN

= 2.4576 MHz)

8 to 128 8 × f

CLKIN

/64 (307.2 kHz @ f

CLKIN

= 2.4576 MHz)

BIPOLAR/UNIPOLAR INPUT

The analog inputs on the AD7705/AD7706 can accept either

unipolar or bipolar input voltage ranges. Bipolar input ranges

do not imply that these parts can handle negative voltages on

their analog inputs; the analog inputs cannot go more negative

than −100 mV to ensure correct operation of these parts. The

input channels are fully differential. As a result, on the AD7705,

the voltage to which the unipolar and bipolar signals on the

AIN(+) input are referenced is the voltage on the respective

AIN(−) input.

AD7705/AD7706

Rev. C | Page 23 of 44

On the AD7706, the voltages applied to the analog input

channels are referenced to the COMMON input. For example, if

AIN1(−) is 2.5 V and AD7705 is configured for unipolar

operation with a gain of 2 and a V

REF

of 2.5 V, the input voltage

range on the AIN1(+) input is 2.5 V to 3.75 V.

If AIN1(−) is 2.5 V and AD7705 is configured for bipolar mode

with a gain of 2 and a V

REF

of 2.5 V, the analog input range on

the AIN1(+) input is 1.25 V to 3.75 V (i.e., 2.5 V ± 1.25 V). If

AIN1(−) is at GND, the part cannot be configured for bipolar

ranges in excess of ±100 mV.

Bipolar or unipolar options are chosen by programming the

/U bit of the setup register. This programs the channel for either

unipolar or bipolar operation. Programming the channel for

either unipolar or bipolar operation does not change the input

signal conditioning, it simply changes the data output coding

and the points on the transfer function where calibrations occur.

REFERENCE INPUT

The AD7705/AD7706 reference inputs, REF IN(+) and REF IN(−),

provide a differential reference input capability. The common-

mode range for these differential inputs is from GND to V

The nominal reference voltage, V

REF

(REF IN(+) − REF IN(−)),

for specified operation is 2.5 V for the AD7705/AD7706 operated

with a V

of 5 V, and 1.225 V for the AD7705/AD7706 operated

with a V

of 3 V. The parts are functional with V

REF

voltages

down to 1 V, but performance will be degraded because the output

noise, in terms of LSB size, is larger. REF IN(+) must be greater

than REF IN(−) for correct operation of the AD7705/AD7706.

Both reference inputs provide a high impedance, dynamic load

similar to the analog inputs in unbuffered mode. The maximum

dc input leakage current is ±1 nA over temperature, and source

resistance might result in gain errors on the part. In this case,

the sampling switch resistance is 5 kΩ typ, and the reference

capacitor, C

REF

, varies with gain. The sample rate on the reference

inputs is f

CLKIN

/64 and does not vary with gain. For gains of 1

and 2, C

REF

is 8 pF; for gains of 16, 32, 64, and 128, it is 5.5 pF,

4.25 pF, 3.625 pF, and 3.3125 pF, respectively.

The output noise performance outlined in

Table 5, Table 6,

Table 7, and Table 8 is for an analog input of 0 V, which

effectively removes the effect of noise on the reference. To

obtain the noise performance shown in the noise tables over the

full input range requires a low noise reference source for the

AD7705/AD7706. If the reference noise in the bandwidth of

interest is excessive, it degrades the performance of the

AD7705/AD7706. In applications where the excitation voltage

for the bridge transducer on the analog input also derives the

reference voltage for the part, the effect of the noise in the

excitation voltage is removed because the application is

ratiometric.

Recommended reference voltage sources for the AD7705/

AD7706 with a V

of 5 V include the AD780, REF43, and

REF192; the recommended reference sources for the AD7705/

AD7706 operated with a V

of 3 V include the AD589 and

AD1580. It is generally recommended to decouple the output of

these references to reduce the noise level further.

DIGITAL FILTERING

The AD7705/AD7706 each contain an on-chip, low-pass digital

filter that processes the output of the Σ-Δ modulator. Therefore,

the parts not only provide the ADC function, but also provide a

level of filtering. There are a number of system differences when

the filtering function is provided in the digital domain, rather

than in the analog domain.

For example, because it occurs after the A/D conversion

process, digital filtering can remove noise injected during the

conversion process, whereas analog filtering cannot do this. In

addition, the digital filter can be made programmable far more

readily than the analog filter. Depending on the digital filter

design, this provides the user with the update rate.

On the other hand, analog filtering can remove noise

superimposed on the analog signal before it reaches the ADC.

Digital filtering cannot do this, and noise peaks riding on

signals near full scale have the potential to saturate the analog

modulator and digital filter, even though the average value of

the signal is within limits.

To alleviate this problem, the AD7705/AD7706 have overrange

headroom built into the Σ-Δ modulator and digital filter that

allows overrange excursions of 5% above the analog input range.

If noise signals are larger than this, consider filtering the analog

input, or reducing the input channel voltage so that its full scale

is half that of the analog input channel full scale. This provides

an overrange capability greater than 100% at the expense of

reducing the dynamic range by 1 bit (50%).

In addition, the digital filter does not provide any rejection at

integer multiples of the digital filter’s sample frequency. However,

the input sampling on the part provides attenuation at multiples

of the digital filter’s sampling frequency so that the unattenuated

bands occur around multiples of the sampling frequency, f

, as

defined in

Table 23. Thus, the unattenuated bands occur at n × f

(where n = 1, 2, 3 . . .). At these frequencies, there are frequency

bands ±f

3 dB

wide (f

3 dB

is the cutoff frequency of the digital filter)

at either side where noise passes unattenuated to the output.

AD7705/AD7706

Rev. C | Page 24 of 44

Filter Characteristics

The AD7705/AD7706 digital filter is a low-pass filter with a

(sinx/x)

response (also called sinc

). The transfer function for

the filter is described in the z-domain by

)(

−

and in the frequency domain by

()

/sin

)(

ffN

×π

×π×

×=

where

N is the ratio of the modulator rate to the output rate.

The phase response is defined by the following equation:

(

)

RadffNH

×−π−=∠ 23

Figure 15 shows the filter frequency response for a cutoff

frequency of 15.72 Hz, which corresponds to a first filter notch

frequency of 60 Hz. The plot is shown from dc to 390 Hz. This

response is repeated at either side of the digital filter’s sample

frequency and at either side of multiples of the filter’s sample

frequency.

The response of the filter is similar to that of an averaging filter,

but with a sharper roll-off. The output rate for the digital filter

corresponds with the positioning of the first notch of the filter’s

frequency response. Thus, for

Figure 15, where the output rate

is 60 Hz, the first notch of the filter is at 60 Hz. The notches of

this (sinx/x)

filter are repeated at multiples of the first notch.

The filter provides attenuation of better than 100 dB at these

notches.

The cutoff frequency of the digital filter is determined by the value

loaded to Bit FS0 and Bit FS1 in the clock register. Programming a

different cutoff frequency via Bit FS0 and Bit FS1 does not alter

the profile of the filter response, but changes the frequency of

the notches. The output update of the part and the frequency of

the first notch correspond.

Because the AD7705/AD7706 contain this on-chip, low-pass

filtering, a settling time is associated with step function inputs,

and data on the output is invalid after a step change until the

settling time has elapsed. The settling time depends on the output

rate chosen for the filter. The settling time of the filter to a full-

scale step input can be up to four times the output data period.

For a synchronized step input using the FSYNC function, the

settling time is three times the output data period.

FREQUENCY (Hz)

–140

–240

GAIN (dB)

60 120 180 240 300 360

–20

–160

–180

–60

–100

–40

–80

–200

–220

–120

01166-015

Figure 15. Frequency Response of AD7705 Filter

Postfiltering

The on-chip modulator provides samples at a 19.2 kHz output rate

with f

CLKIN

at 2.4576 MHz. The on-chip digital filter decimates

these samples to provide data at an output rate that corresponds

to the programmed output rate of the filter. Because the output

data rate is higher than the Nyquist criterion, the output rate for

a given bandwidth satisfies most application requirements. Some

applications, however, might require a higher data rate for a

given bandwidth and noise performance. Applications that need

this higher data rate will require postfiltering following the digital

filtering performed by the AD7705/AD7706.

For example, if the required bandwidth is 7.86 Hz, but the

required update rate is 100 Hz, data can be taken from the

AD7705/AD7706 at the 100 Hz rate, giving a −3 dB bandwidth

of 26.2 Hz. Postfiltering can then be applied to reduce the

bandwidth and output noise to the 7.86 Hz bandwidth level

while maintaining an output rate of 100 Hz.

Postfiltering can also be used to reduce the output noise from

the devices for bandwidths below 13.1 Hz. At a gain of 128 and

a bandwidth of 13.1 Hz, the output rms noise is 450 nV. This is

essentially device noise, or white noise. Because the input is

chopped, the noise has a primarily flat frequency response. By

reducing the bandwidth below 13.1 Hz, the noise in the resultant

pass band is reduced. A reduction in bandwidth by a factor of 2

results in a reduction of approximately 1.25 in the output rms

noise. This additional filtering results in a longer settling time.

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AD7705BRZ-REEL7

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Analog to Digital Converters - ADC 3V/5V 1mW 2-Ch Diff 16-Bit

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AD7705BRZ-REEL7

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