AMIS−30521, NCV70521
http://onsemi.com
19
Charge Pump Failure
The charge pump is an important circuit that guarantees
low R
DS(on)
for all drivers, especially for low supply
voltages. If the supply voltage is too low or external
components are not properly connected to guarantee R
DS(on)
of the drivers, then the bit <CPFAIL> is set in the SPI status
register 0. Also after power−on−reset the charge pump
voltage will need some time to exceed the required
threshold. During that time <CPFAIL> will be set to “1”.
Error Output
This is an open drain digital output to flag a problem to the
external microcontroller. The signal on this output is active
low and the logic combination of:
NOT(ERR
) = <TW> OR <TSD> OR <OVCXij> OR <
OVCYij> OR <OPENi> OR <CPFAIL>
CLR Pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside the AMIS−30521/
NCV70521, the input CLR needs to be pulled to logic 1
during minimum time given by t
CLR
. (See AC Parameters)
This reset function clears all internal registers without the
need of a power−cycle except in sleep mode. The operation
of all analog circuits is depending on the reset state of the
digital, charge pump remains active. Logic 0 on CLR pin
resumes normal operation again.
Sleep Mode
The bit <SLP> in SPI control register 2 is provided to enter
a so−called “sleep mode”. This mode allows reduction of
current−consumption when the motor is not in operation.
The effect of sleep mode is as follows:
• The Drivers are Put in HiZ
• All Analog Circuits are Disabled and in Low−Power
Mode
• All Internal Registers are Maintaining Their Logic
Content
• NXT and DIR Inputs are Ignored
• SPI Communication Remains Possible (Slight Current
Increase During SPI Communication)
• Oscillator and Digital Clocks are Silent, Except During
SPI Communication
Normal operation is resumed after writing logic ’0’ to bit
<SLP>. A startup time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
When the device is in sleep mode and V
BB
becomes lower
than V
BB_min
the device might reset.
SPI INTERFACE
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with the
AMIS−30521/NCV70521. The implemented SPI block is
designed to interface directly with numerous microcontrollers
from several manufacturers. The AMIS−30521/NCV70521
acts always as a Slave and cannot initiate any transmission.
The operation of the device is configured and controlled by
means of SPI registers which are observable for read and/or
write from the Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
DO signal is the output from the Slave
(AMIS−30521/NCV70521), and DI signal is the output
from the Master. A chip select line (CS
) allows individual
selection of a Slave SPI device in a multiple−slave system.
The CS
line is active low. If the AMIS−30521/NCV70521
is not selected, DO is pulled up with the external pull up
resistor. Since AMIS−30521/NCV70521 operates as a Slave
in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out
on the falling edge and samples data in on rising edge of
clock. The Master SPI port must be configured in MODE 0
too, to match this operation. The SPI clock idles low
between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
