ICS650-14
NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER
IDT™ / ICS™
NETWORKING SYSTEM CLOCK 3
ICS650-14 REV G 110409
Key: XI, XO = crystal connections; I = input; I(Pu) = input with pull-up; O = output; P = power supply connection; TI
= tri-level input
External Components
The ICS650-14 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. For a
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
13 CLKA4 O Selectable clock output. See table 1.
14 GND P Connect to ground.
15 SELA1 TI Select pin for CLKA1:4 and CLKA5 outputs. See table 1.
16 VDD P Connect to 3.3 Vor 5 V. Must be same as other VDDs.
17 CLKA3 O Selectable clock output. See table 1.
18 CLKA2 O Selectable clock output. See table 1.
19 SELA0 TI Select pin for CLKA1:4 and CLKA5 outputs. See table 1.
20 SELC TI Select pin for CLKC output. See table 3.
Pin
Number
Pin
Name
Pin
Type
Pin Description
