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PCA9698DGG,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 10 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
Output Port registers
08h 0 0 1 0 0 0 OP0 read/write Output Port register bank 0
09h 0 0 1 0 0 1 OP1 read/write Output Port register bank 1
0Ah 0 0 1 0 1 0 OP2 read/write Output Port register bank 2
0Bh 0 0 1 0 1 1 OP3 read/write Output Port register bank 3
0Ch 0 0 1 1 0 0 OP4 read/write Output Port register bank 4
0Dh 0 0 1 1 0 1 - - reserved for future use
0Eh 0 0 1 1 1 0 - - reserved for future use
0Fh 0 0 1 1 1 1 - - reserved for future use
Polarity Inversion registers
10h 0 1 0 0 0 0 PI0 read/write Polarity Inversion register bank 0
11h 0 1 0 0 0 1 PI1 read/write Polarity Inversion register bank 1
12h 0 1 0 0 1 0 PI2 read/write Polarity Inversion register bank 2
13h 0 1 0 0 1 1 PI3 read/write Polarity Inversion register bank 3
14h 0 1 0 1 0 0 PI4 read/write Polarity Inversion register bank 4
15h 0 1 0 1 0 1 - - reserved for future use
16h 0 1 0 1 1 0 - - reserved for future use
17h 0 1 0 1 1 1 - - reserved for future use
I/O Configuration registers
18h 0 1 1 0 0 0 IOC0 read/write I/O Configuration register bank 0
19h 0 1 1 0 0 1 IOC1 read/write I/O Configuration register bank 1
1Ah 0 1 1 0 1 0 IOC2 read/write I/O Configuration register bank 2
1Bh 0 1 1 0 1 1 IOC3 read/write I/O Configuration register bank 3
1Ch 0 1 1 1 0 0 IOC4 read/write I/O Configuration register bank 4
1Dh 0 1 1 1 0 1 - - reserved for future use
1Eh 0 1 1 1 1 0 - - reserved for future use
1Fh 0 1 1 1 1 1 - - reserved for future use
Mask Interrupt registers
20h 1 0 0 0 0 0 MSK0 read/write Mask interrupt register bank 0
21h 1 0 0 0 0 1 MSK1 read/write Mask interrupt register bank 1
22h 1 0 0 0 1 0 MSK2 read/write Mask interrupt register bank 2
23h 1 0 0 0 1 1 MSK3 read/write Mask interrupt register bank 3
24h 1 0 0 1 0 0 MSK4 read/write Mask interrupt register bank 4
25h 1 0 0 1 0 1 - - reserved for future use
26h 1 0 0 1 1 0 - - reserved for future use
27h 1 0 0 1 1 1 - - reserved for future use
Miscellaneous
28h 1 0 1 0 0 0 OUTCONF read/write output structure configuration
29h 1 0 1 0 0 1 ALLBNK read/write control all banks
2Ah 1 0 1 0 1 0 MODE read/write PCA9698 mode selection
Table 3. Register summary
…continued
Reg # D5 D4 D3 D2 D1 D0 Name Type Function
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 11 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.1 IP0 to IP4 - Input Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to
these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.
7.4.2 OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
Legend: * default value ‘X’ determined by the externally applied logic level.
Address Register Bit Symbol Access Value Description
00h IP0 7 to 0 I0[7:0] R XXXX XXXX* Input Port register bank 0
01h IP1 7 to 0 I1[7:0] R XXXX XXXX* Input Port register bank 1
02h IP2 7 to 0 I2[7:0] R XXXX XXXX* Input Port register bank 2
03h IP3 7 to 0 I3[7:0] R XXXX XXXX* Input Port register bank 3
04h IP4 7 to 0 I4[7:0] R XXXX XXXX* Input Port register bank 4
Table 5. OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
08h OP0 7 to 0 O0[7:0] R/W 0000 0000* Output Port register bank 0
09h OP1 7 to 0 O1[7:0] R/W 0000 0000* Output Port register bank 1
0Ah OP2 7 to 0 O2[7:0] R/W 0000 0000* Output Port register bank 2
0Bh OP3 7 to 0 O3[7:0] R/W 0000 0000* Output Port register bank 3
0Ch OP4 7 to 0 O4[7:0] R/W 0000 0000* Output Port register bank 4
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 12 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.3 PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register.
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
7.4.4 IOC0 to IOC4 - I/O Configuration registers
These registers configure the direction of the I/O pins.
Cx[y] = 0: The corresponding port pin is an output.
Cx[y] = 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
10h PI0 7 to 0 P0[7:0] R/W 0000 0000* Polarity Inversion register bank 0
11h PI1 7 to 0 P1[7:0] R/W 0000 0000* Polarity Inversion register bank 1
12h PI2 7 to 0 P2[7:0] R/W 0000 0000* Polarity Inversion register bank 2
13h PI3 7 to 0 P3[7:0] R/W 0000 0000* Polarity Inversion register bank 3
14h PI4 7 to 0 P4[7:0] R/W 0000 0000* Polarity Inversion register bank 4
Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
18h IOC0 7 to 0 C0[7:0] R/W 1111 1111* I/O Configuration register bank 0
19h IOC1 7 to 0 C1[7:0] R/W 1111 1111* I/O Configuration register bank 1
1Ah IOC2 7 to 0 C2[7:0] R/W 1111 1111* I/O Configuration register bank 2
1Bh IOC3 7 to 0 C3[7:0] R/W 1111 1111* I/O Configuration register bank 3
1Ch IOC4 7 to 0 C4[7:0] R/W 1111 1111* I/O Configuration register bank 4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

PCA9698DGG,512

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Buy PCA9698DGG,512
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders I2C I/O EXPANDER GP
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