10©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
2.5V LVPECL Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both signals must meet the V
IN
and V
IH
input requirements. Figures 3A to 3D show interface
examples for the IN/nIN with built-in 50 termination input driven
by the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the vendor
of the driver component to confirm the driver termination
requirements.
Figure 3A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 3C. IN/nIN Input with Built-In 50
Driven by a CML Driver with Open Collector
Figure 3B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure 3D. IN/nIN Input with Built-In 50
Driven by a CML Driver with Built-In 50
Pullup
11©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Recommendations for Unused Output Pins
Outputs:
LVPECL Outputs
All unused LVPECL output pairs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
2.5V Differential Input with Built-In 50 Termination Unused Input Handling
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and complement of the
unused input as shown in Figure 4A.
Figure 4A. Unused Input Handling
3.3V Differential Input with Built-In 50 Termination Unused Input Handling
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and complement of the
unused input as shown in Figure 4B.
Figure 4B. Unused Input Handling
Receiver
With
Built-In
50Ω
IN
nIN
VT
2.5V
2.5V
R2
680
R1
680
Receiver
With
Built-In
50Ω
IN
nIN
VT
3.3V
3.3V
R2
1k
R1
1k
12©2016 Integrated Device Technology, Inc Revision A February 5, 2016
8S58035I Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_

8S58035AKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:1 MUX WITH 6 OUTPUT FANOUT BUFFER
Lifecycle:
New from this manufacturer.
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