IDT
®
Four Output Differential Buffer for PCI Express 1250C—06/28/12
Advance Information
ICS9DBL411A
Four Output Differential Buffer for PCI Express
6
AC Electrical Characteristics - DIF Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate t
SLR
Differential Measurement 1 2.5 V/ns 1,2
Falling Edge Slew Rate t
FLR
Differential Measurement 1 2.5 V/ns 1,2
Slew Rate Variation t
SLVAR
Single-ended Measurement 20 % 1
Maximum Output Voltage V
HIGH
Includes overshoot 1150 mV 1
Minimum Output Voltage V
LOW
Includes undershoot -300 mV 1
Differential Voltage Swing V
SWING
Differential Measurement 1200 mV 1
Crossing Point Voltage V
XABS
Single-ended Measurement 300 550 mV 1,3,4
Crossing Point Variation V
XABSVAR
Single-ended Measurement 140 mV 1,3,5
D
CYCDIS0
Differential Measurement,
fIN<=100MHz
0.5 % 1,6
D
CYCDIS1
Differential Measurement
100MHz < fIN<=267MHz
+5 % 1,6
D
CYCDIS2
Differential Measurement,
fIN>267MHz
+7 % 1,6
DIF Jitter - Cycle to Cycle DIFJ
C2C
Differential Measurement,
Additive
25 ps 1
DIF[3:0] Skew DIF
SKEW
Differential Measurement 50 ps 1
Propagation Delay t
PD
Input to output Delay 2.5 3.5 ns 1
PCIe Gen2 Phase Jitter -
Addtive
t
phase_addHI
1.5MHz < fIN < Nyquist (50MHz) 0.8 ps rms 1
PCIe Gen2 Phase Jitter -
Addtive
t
phase_addLO
10KHz < fIN < 1.5MHz 0.1 ps rms 1
Notes on Electrical Characteristics:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
8
Maximum input voltage is not to exceed maximum VDD
6
Tthis is the figure refers to the maximum distortion of the input wave form.
5
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
7
Operation under these conditions is neither implied, nor guaranteed.
Duty Cycle Distortion