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MC74VHC1G00DFT2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 21
1 Publication Order Number:
MC74VHC1G00/D
MC74VHC1G00
Single 2-Input NAND Gate
The MC74VHC1G00 is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The MC74VHC1G00 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G00 to be used to interface 5.0 V circuits to
3.0 V circuits.
Features
• High Speed: t
PD
= 3.0 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 1 mA (Max) at T
A
= 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 56
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Pinout (Top View)
V
CC
IN B
IN A
OUT Y
GND
Figure 2. Logic Symbol
OUT Y
&
1
2
34
5
IN B
IN A
PIN ASSIGNMENT
1
2
3 GND
IN B
IN A
4
5V
CC
OUT Y
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
H
H
H
L
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
http://onsemi.com
1
5
V1 M G
G
1
5
V1M G
M
G
V1 = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
MC74VHC1G00
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage *0.5 to +7.0 V
V
IN
DC Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage *0.5 to V
CC
+0.5 V
I
IK
DC Input Diode Current −20 mA
I
OK
DC Output Diode Current ±20 mA
I
OUT
DC Output Sink Current ±12.5 mA
I
CC
DC Supply Current per Supply Pin ±25 mA
T
STG
Storage Temperature Range *65 to +150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction Temperature Under Bias +150 °C
q
JA
Thermal Resistance SC70−5/SC−88A (Note 1)
TSOP−5
350
230
°C/W
P
D
Power Dissipation in Still Air at 85°C SC70−5/SC−88A
TSOP−5
150
200
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 5) ±500 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage 0.0 V
CC
V
T
A
Operating Temperature Range *55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V $ 0.3 V
V
CC
= 5.0 V $ 0.5 V
0
0
100
20
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
NORMALIZED FAILURE RATE
TIME, YEARS
T
J
= 130°C
T
J
= 120°C
T
J
= 110°C
T
J
= 100°C
T
J
= 90°C
T
J
= 80°C
MC74VHC1G00
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3
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
(V)
T
A
= 255C T
A
v 855C *555C to 1255C
Uni
t
Min Typ Max Min Max Min Max
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
IN
Maximum Input
Leakage Current
V
IN
= 5.5 V or GND 0 to
5.5
±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND 5.5 1.0 10 40
mA
AC ELECTRICAL CHARACTERISTICS Input t
r
= t
f
= 3.0 ns
Symbo
l
Parameter Test Conditions
T
A
= 255C T
A
v 855C *555C to 1255C
Uni
t
Min Typ Max Min Max Min Max
t
PLH
,
t
PHL
Maximum Propagation
Delay, Input A or B to Y
V
CC
= 3.3 $ 0.3 V C
L
= 15 pF
C
L
= 50 pF
4.5
5.6
7.9
11.4
9.5
13.0
11.0
15.5
ns
V
CC
= 5.0 $ 0.5 V C
L
= 15 pF
C
L
= 50 pF
3.0
3.8
5.5
7.5
6.5
8.5
8.0
10.0
C
IN
Maximum Input
Capacitance
5.5 10 10 10 pF
C
PD
Power Dissipation Capacitance (Note 6)
Typical @ 25°C, V
CC
= 5.0 V
10 pF
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
P1-P3P4-P6

MC74VHC1G00DFT2G

Mfr. #:
Buy MC74VHC1G00DFT2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates 2-5.5V Single 2-Input NAND
Lifecycle:
New from this manufacturer.
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