Advanced Clock Drivers Devices
4 Freescale Semiconductor
MPC9315
Table 4. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
÷ 2 V
MM ESD (Machine Model) 200 V
HBM ESD (Human Body Model) 2000 V
LU Latch-Up 200 mA
C
PD
Power Dissipation Capacitance 10 pF Per output
C
IN
Input Capacitance 4.0 pF Inputs
Table 5. DC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= -40° to 85°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
V
OH
Output High Voltage 2.4 V I
OH
= –24 mA
(1)
1. The MPC9315 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
V
OL
Output Low Voltage 0.55
0.30
V
V
I
OL
= 24 mA
(1)
I
OL
= 12 mA
Z
OUT
Output Impedance 14 - 17
I
IN
Input Current
(2)
2. Inputs have pull-up or pull-down resistors affecting the input current.
±200 µA V
IN
= V
CC
or
GND
I
CCA
Maximum PLL Supply Current 3.5 7.0 mA V
CCA
Pin
I
CCQ
Maximum Quiescent Supply Current 1.0 mA All V
CC
Pins
Advanced Clock Drivers Devices
Freescale Semiconductor 5
MPC9315
Table 6. AC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= -40° to 85°C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
ref
Input Frequency ÷1 feedback
÷2 feedback
÷4 feedback
PLL bypass mode
100
(2)
37.50
18.75
0
2. The VCO range in ÷1 feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100 f
VCO
160 MHz. Please see
next revision of the MPC9315 for improved VCO frequency range.
160
80
40
TBD
MHz
MHz
MHz
MHz
PLL locked
PLL locked
PLL locked
V
CCA
= GND
f
VCO
VCO Lock Range 75
(2)
160 MHz
f
MAX
Maximum Output Frequency ÷1 output
÷2 output
÷4 output
75
37.50
18.75
160
80
40
MHz
MHz
MHz
f
refDC
Reference Input Duty Cycle 25 75 %
t
r
, t
f
CLK0, CLK1 Input Rise/Fall Time 1.0 ns 0.8 to 2.0 V
t
()
Propagation Delay CLK0 or CLK1 to FB
(Static Phase Offset)
-150 +150 ps PLL locked
t
SK()
Output-to-Output Skew Within one bank
Any output
80
120
ps
ps
DC Output Duty Cycle 45 50 55 %
t
r
, t
f
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V
t
PLZ, HZ
Output Disable Time 10 ns
t
PZL, LZ
Output Enable Time 10 ns
BW PLL closed loop bandwidth ÷1 feedback
÷2 feedback
÷4 feedback
TBD
2.0 - 20
0.6 - 6.0
MHz
MHz
MHz
t
JIT(CC)
Cycle-to-Cycle Jitter (1σ) 10 22 ps RMS value
t
JIT(PER)
Period Jitter (1σ) 8.0 15 ps RMS value
t
JIT()
I/O Phase Jitter (1σ) 8.0 - 25
(3)
3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
TBD ps RMS value
t
LOCK
Maximum PLL Lock Time 1.0 ms
Table 7. DC Characteristics (V
CC
= 2.5 V ± 5%, T
A
= -40° to 85°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input High Voltage 1.7 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.7 V LVCMOS
V
OH
Output High Voltage 1.8 V I
OH
= –15 mA
(1)
1. The MPC9315 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
V
OL
Output Low Voltage 0.6 V I
OL
= 15 mA
Z
OUT
Output Impedance 17 - 20
I
IN
Input Current
(2)
2. Inputs have pull-up or pull-down resistors affecting the input current.
±200 µA V
IN
= V
CC
or
GND
I
CCA
Maximum PLL Supply Current 2.0 5.0 mA V
CCA
Pin
I
CCQ
Maximum Quiescent Supply Current 1.0 mA All V
CC
Pins
Advanced Clock Drivers Devices
6 Freescale Semiconductor
MPC9315
Table 8. AC Characteristics (V
CC
= 2.5 V ± 5%, T
A
= -40° to 85°C)
(1)
1. AC characteristics apply for parallel output termination of 50 to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
ref
Input Frequency ÷2 feedback
÷4 feedback
PLL bypass mode
37.50
18.75
0
80
40
TBD
MHz
MHz
MHz
PLL locked
PLL locked
VCCA = GND
f
VCO
VCO Lock Range 75
(2)
2. ÷1 feedback is responsible for V
CC
= 2.5 V operation. Please see application section for I/O jitter versus VCO frequency characteristics.
160
(2)
MHz
f
MAX
Maximum Output Frequency ÷1 output
÷2 output
÷4 output
75
37.50
18.75
160
80
40
MHz
MHz
MHz
f
refDC
Reference Input Duty Cycle 25 75 %
t
r
, t
f
CLK0, CLK1 Input Rise/Fall Time 1.0 ns 0.7 to 1.7 V
t
()
Propagation Delay CLK0 or CLK1 to FB
(Static Phase Offset)
-150 +150 ps PLL locked
t
SK()
Output-to-Output Skew Within one bank
Any output
80
120
ps
ps
DC Output Duty Cycle 45 50 55 %
t
r
, t
f
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V
t
PLZ, HZ
Output Disable Time 12 ns
t
PZL, LZ
Output Enable Time 12 ns
BW PLL closed loop bandwidth ÷2 feedback
÷4 feedback
1.0 - 10
0.4 - 3.0
MHz
MHz
t
JIT(CC)
Cycle-to-Cycle Jitter (1σ) 10 22 ps RMS value
t
JIT(PER)
Period Jitter (1σ) 8.0 15 ps RMS value
t
JIT()
I/O Phase Jitter (1σ) 10 - 25
(3)
3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
TBD ps RMS value
t
LOCK
Maximum PLL Lock Time 1.0 ms

MPC9315AC

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products FSL 1-8 LVCMOS PLL Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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