L6521 Datasheet L6521TR, L6521, L6520TR | P10-P12

Functions description L6520, L6521

10/19 Doc ID 16998 Rev 3

5.3 Ignition

During the ignition sequence the output frequency ramps down from the programmed

preheating frequency to the fixed run frequency with a fixed rate df

IGN

/dt of - 2.75 kHz/ms. If

the instant start is selected, the frequency ramps down from 85 kHz to 46.6 kHz (typ.) with

the same rate.

The current control circuit limits the maximum lamp voltage (OCPH) in case of old or broken

lamp and it is able to control the lamp current in case of inductor saturation (CSC).

The ignition phase lasts for maximum 200 ms. If the Run frequency is not reached during

ignition phase, the IC is turned off (latched).

5.4 Run mode

The run frequency is internally set to 46.6 kHz.

The HSD and LSD pins drive respectively the high side and the low side switches. The

potential isolation to the high side switch is realized by a pulse transformer. The HSD and

LSD drivers are able to manage the inductive load represented by the primary side of the

pulse transformer.

Between the turn-off of one driver and turn-on of the other one there is a dead time

automatically optimized accordingly to the kind of the half bridge switches (MOS or BJT) to

ensure the maximum reliability. The CCC protects the circuit against over currents, choke

saturation and hard switching events.

5.5 Storage time compensation network

In all the operating states (preheating, ignition and run mode), the storage time

compensation ensures the application of the fixed dead time (t

DEAD

, 1.42 us typ.) once the

BJT's collector current is effectively reduced to zero. The t

DEAD

is the sum of a fixed time,

generated by internal logic and the propagation delay of PWM_det comparator.

The voltage level of the middle point of the half bridge is monitored through the PWM_det

pin: the high side switch is turned on after a fixed dead time from the instant when the

voltage on the PWM_det pin is above 2.65 V. The time between the falling edge of pin LSD

and the rising edge of HSD is recorded in order to set the same dead time between the

falling edge of pin HSD and the rising edge of pin LSD.

The minimum duration of the resulting ON time is internally limited to 1 µs. This condition

can last for a maximum time equal to 200 ms. After this time the IC is shut down (latched).

The PWM_det pin embeds a 5 V (typ.) clamping zener, allowing the connection between the

half bridge middle point and the pin itself by means of a limiting resistor.

When driving MOSFET no storage time is present, therefore the resulting dead time is equal

to (1.42 µs).

L6520, L6521 Functions description

Doc ID 16998 Rev 3 11/19

5.6 Current control circuit (CCC)

The current control circuit (CCC) is a sophisticated circuit able to protect the ballast against

any possible failure. It limits the maximum lamp voltage during ignition (OCPH), overcurrent

protection (OCPL) during run mode, chokes saturation control (CSC) and hard switching

protection (HSP). The control circuit senses the voltage on HBCS pin and PWM_det pin.

Figure 3 on page 13 shows the CCC protections active in each operating mode (preheating,

ignition and run):

5.6.1 Hard switching protection (HSP)

If the voltage on PWM_det pin is higher than 2.35 V at the moment the LS driver turns on,

an up-down event counter is increased and an internal timer is started. Without hard

switching events, the counter decreases at every cycle and the timer is reset when 0 is

reached. If the events counter value is higher than 0 after 200 ms from the detection of the

first event, then the IC is turned off (latched).

5.6.2 Overcurrent protection (OCPH) during ignition mode

The protection results in lamp voltage limitation during ignition. In this phase three

thresholds are active (THL, THM and THH):

If the first threshold is crossed the frequency is increased by 1 kHz during the next cycle.

The interval between the crossings of the two lower thresholds (THL and THM) is used as

an indication of the slope of the half bridge current: if this interval is longer than t1 = 510 ns

the event is considered “slow” and the frequency is increased by another 1 kHz/cycle during

the next cycle. If the interval is shorter than t1 = 510 ns but longer than t2 = 255 ns, the

event is considered “fast” and the frequency is increased by another 2 kHz/cycle during the

next cycle.

If no further threshold crossing is detected, the frequency is decreased with a fixed rate

equal to df

CCC

/dt = - 500 Hz/ms, until the frequency at which the lowest threshold was

crossed firstly is reached; then, the decreasing ratio becomes again df

IGN

/dt.

If the run frequency has not been reached within 200 ms after the lower threshold was

crossed the first time, the IC is turned off (latched).

A leading edge blanking of 255 ns is active.

5.6.3 Overcurrent protection (OCPL) during run mode

The behavior of the OCPL is similar to the OCPH but with reduced thresholds (TLL, TLM

and TLH) since the current involved in this phase is smaller. If no further threshold crossing

is detected, the frequency is decreased with a fixed rate equal to d

fCCC

= - 500 Hz/ms,

until the run frequency is reached.

If the run frequency has not been reached after 200 ms from when the lower threshold was

crossed the first time, the IC is turned off (latched).

A leading edge blanking of 255 ns is active.

Functions description L6520, L6521

12/19 Doc ID 16998 Rev 3

5.6.4 Choke saturation control (CSC) during ignition and run mode

The same thresholds used to detect OCPH and OCPL are active.

The control is still based on the time between two consecutive thresholds but its behavior is

different with respect to the OCPH/OCPL detection to take into account the increase of dI/dt

when the inductor is saturating. When either the two lower thresholds are crossed in a time

shorter than 255 ns or the higher threshold is crossed, the LS driver is immediately turned

off and the time between the LS turn on and the instant when the second threshold (THM or

TLM) is crossed is used to calculate the new (higher) frequency.

If this new frequency is higher than 100 kHz then the new frequency will be set at 100 kHz.

The frequency is then decreased with a fixed df/dt equal to df

CCC

/dt = - 500 Hz/ms, until the

frequency at which the first threshold was crossed is reached. Then, the decreasing ratio

becomes again df

IGN

/dt during ignition whereas, during run mode, the df

CCC

/dt decreasing

ratio is maintained until run frequency is reached.

If the run frequency has not been reached after 200 ms from when the lower threshold was

crossed the first time, the IC is turned off (latched).

A leading edge blanking of 255 ns is active.

5.7 End of life (EOL)

An embedded window comparator can be used to detect the end of life (EOL) when the

lamp is directly connected to ground (lamp to ground configuration).

After the ignition sequence, the EOL window comparator becomes active. When the voltage

at EOL pin goes outside the limits of this comparator a 1.5 s timer is started. If the EOL pin

voltage does not return inside the allowed range before the end of the timer, the IC is shut

down (latched).

The EOL pin is biased to the center of the window comparator by means of an OTA (2.5 V

typ. with +/- 1.5 V typ. window), having a current capability equal to 9.1 µA (typ.).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

L6521

Mfr. #:

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Display Drivers & Controllers LV Smart Ballast CTR Half Bridge BJT FET

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