6 CGD15HB62LP Rev. A, 07-2016
• PWM Signals: High side and low side PWM must be differential signals
4
. The termination impedance of
the differential receiver is 250 Ω. A reference single-ended to differential converter is available as an
optimized companion product. Overlap protection is provided to prevent both the high side and low side
gates from turning on simultaneously. The overlap protection should not be used as a dead time
generator.
• FAULT Signal: The fault signal is a differential output
4
with a maximum drive strength of 20mA. A high
signal (positive line > negative line) means there are no fault conditions for either gate driver channel.
This signal will be low if a UVLO or over-current fault is detected on either channel. See below for further
description for what the individual faults indicate.
• UVLO Fault: The UVLO circuit detects when the output rails of the isolated DC/DC converter falls below
safe operating conditions for the gate driver. A UVLO fault indicates that the potential between the split
output rails has fallen below the UVLO active level. The gate for the channel where the fault occurred will
be pulled low through R
G
for the duration of the fault regardless of the PWM input signal. The fault will
automatically clear once the potential has risen above the UVLO inactive level. There is hysteresis for
this fault to ensure safe operating conditions, and the inactive and active regions can be configured
through on-board resistors. The UVLO faults for both channels are combined along with the over-current
fault in the FAULT output signal.
• Over-Current Fault: An over-current fault is an indication of an over-current event in the SiC power
module. The over-current protection circuit measures the drain-source voltage, and the fault will indicate
if this voltage has risen above a level corresponding to the safe current limit. A drain sense connection
is provided by quick-connect spade connectors for both high side and low side. The low side drain
connection can optionally be connected on-board to the high side source through jumper RT19. When a
fault has occurred the corresponding gate driver channel will be disabled, and the gate will be pulled
down through a soft-shutdown resistor, R
SS
3
.
The drain-source limit can be configured through on-board
resistors. The over-current protection is enabled by default, but it can be disabled by pulling the OC-EN
pin low. The gate driver will operate correctly with this protection disabled. The over-current fault is
latched upon detection and must be cleared by the user with a low pulse of at least 2.5 ns on the OC-EN
signal.
• RTD Signal: RTD output is a differential signal
4
that measures the resistance of the RTD integrated into
XAS325M12HM2 modules. The signal is a 50 kHz PWM that encodes the resistance of the RTD. The
minimum and maximum duty cycles are 5% and 95% respectively to guarantee a signal is always present.
The approximate temperature of the module can be determined from this resistance
5
. The module
temperature can be calculated using the formula,
= 5.42 ∗
(
)
− 244 ° .
• PS-Dis Signal: PS-DIS signal disables the output of the isolated DC/DC converters for the two channels.
It is a single-ended input that must be pulled low to turn off the power supplies. This can be used for
startup sequencing.
4
A single-ended to differential converter for both input and output is available as an optimized companion product.
5
See CAS325M12HM2 with Optional RTD Application Note for further description of the RTD measurements.
