22
LTC1735
1735fc
The I
TH
series R
C
–C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1µs
to 10µs will produce output voltage and I
TH
pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
may not be within the bandwidth of the feedback loop, so
the standard second-order overshoot/DC ratio cannot be
used to determine phase margin. The gain of the loop will
be increased by increasing R
C
and the bandwidth of the
loop will be increased by decreasing C
C
. If R
C
is increased
by the same factor that C
C
is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately (25)(C
LOAD
). Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning
Fast load transient response, limited board space and low
cost are requirements of microprocessor power supplies.
APPLICATIO S I FOR ATIO
WUU
U
Active voltage positioning improves transient response
and reduces the output capacitance required to power a
microprocessor where a typical load step can be from 0.2A
to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the
microprocessor must be held to about ±0.1V of nominal
in spite of these load current steps. Since the control loop
cannot respond this fast, the output capacitors must
supply the load current until the control loop can respond.
Capacitor ESR and ESL primarily determine the amount of
droop or overshoot in the output voltage. Normally, sev-
eral capacitors in parallel are required to meet micropro-
cessor transient requirements.
Active voltage positioning is a form of deregulation. It sets
the output voltage high for light loads and low for heavy
loads. When load current suddenly increases, the output
voltage starts from a level higher than nominal so the
output voltage can droop more and stay within the speci-
fied voltage range. When load current suddenly decreases
the output voltage starts at a level lower than nominal so
the output voltage can have more overshoot and stay
within the specified voltage range. Less output capaci-
tance is required when voltage positioning is used be-
cause more voltage variation is allowed on the output
capacitors.
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735 and two resistors
connected to the I
TH
pin. An input voltage offset is intro-
duced when the error amplifier has to drive a resistive load.
This offset is limited to ±30mV at the input of the error
amplifier. The resulting change in output voltage is the
product of input offset and the feedback voltage divider
ratio.
Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R4 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R4, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1735 reference accu-
racy is ±1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result-
ing setpoint accuracy is ±2% so the output transient
23
LTC1735
1735fc
APPLICATIO S I FOR ATIO
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16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
OSC
RUN/SS
I
TH
FCB
SGND
V
OSENSE
SENSE
SENSE
+
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
U1
LTC1735
C2
0.1µF
C8
0.22µF
C4
100pF
C5
47pF
C3
100pF
R2
100k
R1
27k
R5
0.003
GND
V
OUT
1.5V
15A
V
IN
7.5V TO
24V
GND
C6
1000pF
C1
39pF
+
C10
4.7µF
10V
C9
1µF
5V (OPTIONAL)
C11
330pF
C19
1µF
+
C15 TO
C18
180µF
4V
C7
0.1µF
M1
FDS6680A
M2, M3
FDS6680A
×2
C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
M1 TO M3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1735CS
1735 F08
D1
CMDSH-3
R6
10k
R7
11.5k
D2
MBRS340
C12 TO C14
10µF
35V
L1
1µH
R4
100k
R3
680k
Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning
voltage cannot exceed ±0.082V. At V
OUT
= 1.5V, the
maximum output voltage change controlled by the I
TH
pin
would be:
∆=
=
±
V
Input Offset V
V
V
V
mV
OSENSE
OUT
REF
.•.
.
003 15
08
56
With the optimum resistor values at the I
TH
pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position-
ing provides an additional ±56mV to the allowable tran-
sient voltage on the output capacitors, a 68% improve-
ment over the ±82mV allowed without active voltage
positioning.
The next step is to calculate the scale factor for V
ITH
, the
I
TH
pin voltage. The V
ITH
scale factor reflects the I
TH
pin
voltage required for a given load current. V
ITH
controls the
peak sense resistor voltage, which represents the DC
output current plus one half of the peak-to-peak inductor
current. The no load to full load V
ITH
range is from 0.3V to
2.4V, which controls the sense resistor voltage from 0V to
the V
SENSE(MAX)
voltage of 75mV. The calculated V
ITH
scale factor with a 0.003 sense resistor is:
V ScaleFactor
V Range Sense sistor Value
V
VV
V
VA
ITH
ITH
SENSE MAX
=
==
•Re
(. . ) .
.
./
()
24 03 0003
0 075
0 084
V
ITH
at any load current is:
VI
I
V ScaleFactor
V Offset
ITH OUTDC
L
ITH
ITH
=+
+
2
24
LTC1735
1735fc
At full load current:
VA
A
VA V
V
ITH MAX
PP
()
•. / .
.
=+
+
=
15
5
2
0 084 0 3
177
At minimum load current:
VA
A
VA V
V
ITH MIN
PP
()
.•./.
.
=+
+
=
02
2
2
0 084 0 3
040
In this circuit, V
ITH
changes from 0.40V at light load to
1.77V at full load, a 1.37V change. Notice that I
L
, the
peak-to-peak inductor current, changes from light load to
full load. Increasing the DC inductor current decreases the
permeability of the inductor core material, which de-
creases the inductance and increases I
L
. The amount of
inductance change is a function of the inductor design.
To create the ±30mV input offset, the gain of the error
amplifier must be limited. The desired gain is:
A
V
Input OffsetError
V
V
V
ITH
=
==
137
2003
22 8
.
(. )
.
Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:
R
A
Error Amplifier g mS
k
ITH
V
m
===
22 8
13
17 54
.
.
.
To center the output voltage variation, V
ITH
must be
centered so that no I
TH
pin current flows when the output
voltage is nominal. V
ITH(NOM)
is the average voltage be-
tween V
ITH
at maximum output current and minimum
output current:
V
VV
V
VV
VV
ITH NOM
ITH MAX ITH MIN
ITH MIN()
() ()
()
.–.
..
=+
=+=
2
177 040
2
0 40 1 085
APPLICATIO S I FOR ATIO
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The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R4 that sources
current into the I
TH
pin and resistor R1 that sinks current
to SGND.
To calculate the resistor values, first determine the ratio
between them:
V
INTVCC
is equal to V
EXTVCC
or 5.2V if EXTV
CC
is not used.
Resistor R4 is:
Rk R k
ITH
4 1 3 79 1 17 54 84 0=+ = + =() (. ). .
Resistor R1 is:
R
kR
k
k
k
ITH
1
1 3 79 1 17 54
379
22 17=
+
=
+
=
() (. ).
.
.
Unfortunately, PCB noise can add to the voltage developed
across the sense resistor, R5, causing the I
TH
pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R5 so the
calculated values of R1 and R4 may need to be adjusted to
achieve the required results. Since PCB noise is a function
of the layout, it will be the same on all boards with the same
layout.
Figures 9 and 10 show the transient response before and
after active voltage positioning is implemented. Notice
that active voltage positioning reduced the transient re-
sponse from almost 200mV
P-P
to a little over 100mV
P-P
.
Refer to Design Solutions 10 for more information about
active voltage positioning.

LTC1735CF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Eff Sync Buck Sw Reg
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