NVD5C464NT4G

NVD5C464N
www.onsemi.com
4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. GatetoSource vs. Total Charge
V
DS
, DRAINTOSOURCE VOLTAGE (V) Q
G
, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
R
G
, GATE RESISTANCE (W)
V
SD
, SOURCETODRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
V
DS
, DRAINTOSOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
C, CAPACITANCE (pF)
V
GS
, GATETOSOURCE VOLTAGE (V)
t, TIME (ns)
I
S
, SOURCE CURRENT (A)
I
D
, DRAIN CURRENT (A)
I
PEAK
, (A)
V
GS
= 0 V
T
J
= 25°C
f = 1 MHz
C
ISS
C
OSS
C
RSS
V
DS
= 32 V
T
J
= 25°C
I
D
= 30 A
Q
GS
Q
GD
V
GS
= 10 V
V
DS
= 32 V
I
D
= 17 A
t
d(off)
t
d(on)
t
f
t
r
T
J
= 125°C T
J
= 25°C T
J
= 55°C
T
J
(initial) = 100°C
T
J
(initial) = 25°C
R
DS(on)
Limit
Thermal Limit
Package Limit
1 ms
10 ms
T
C
= 25°C
V
GS
10 V
Single Pulse
1
100
1000
10000
0 5 10 20 25
0
2
4
6
8
10
02 4 10
1
100
1000
1 10 100
0.1
100
0.3 0.4 0.5 0.6 1.0
1000
1 10 1000.1
100
10
1
0.1
1
10
100
0.00001 0.001 0.010.0001
30 40 12 20
0.7 0.8 0.9
1000
10 ms
0.5 ms
V
GS
= 0 V
15 35 8 16
1
3
5
7
9
10
10
10
1
61418
NVD5C464N
www.onsemi.com
5
TYPICAL CHARACTERISTICS
0.01
0.1
1
10
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 10000
Figure 13. Thermal Characteristics
PULSE TIME (sec)
R(t) (°C/W)
Single Pulse
50% Duty Cycle
20%
10%
5%
2%
1%
1000
ORDERING INFORMATION
Order Number Package Shipping
NVD5C464NT4G DPAK
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
1
2
3
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4
b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
A 0.086 0.094 2.18 2.38
b 0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c 0.018 0.024 0.46 0.61
e 0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −− 0.040 −−− 1.01
L 0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒ
mm
inches
Ǔ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H 0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2
GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
e
BOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
DPAK SINGLE GAUGE SURFACE MOUNT
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2

NVD5C464NT4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET T6 40V SL DPAK
Lifecycle:
New from this manufacturer.
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