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CY7C1011DV33-10BVIT
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
CY7C101
1DV33
Document Number: 38-05609 Rev
. *H
Page 10 of 17
Figure 9. W
rite Cycle No. 3 (W
E
Controlled, OE
HI
GH During W
rite)
[20, 21]
Figure 10. Write Cycle No. 4
(WE
Controlled, OE
LOW)
[23]
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE
22
BHE
,B
L
E
t
HD
t
SD
t
SCE
t
HA
t
AW
t
PWE
t
WC
t
BW
DATA
I/O
ADDRESS
CE
WE
BHE
,
BLE
t
SA
t
LZWE
t
HZWE
NOTE
22
BHE
,B
L
E
Notes
20.
Dat
a I/O is high-impedance if OE
or BHE
and/
or BLE
= V
IH
.
21.
If CE
goes HIGH simultaneously with
WE
going HIGH, the output remains in a high-imped
ance state.
22.
During this perio
d the I/Os are in the output state and inp
ut signals should not be applied.
23.
The minimum write pulse wid
th for Write Cycle No. 4 (WE
controlled, OE
LOW) should be the sum of t
SD
and t
HZWE
.
CY7C101
1DV33
Document Number: 38-05609 Rev
. *H
Page 1
1 of 17
T
ruth T
able
CE
OE
WE
BLE
BHE
I/O
0
–I/O
7
I/O
8
–I/O
15
Mode
Power
H
XXXX
H
i
g
h
Z
H
i
g
h
Z
P
o
w
e
r
-
d
o
w
n
S
t
andby (I
SB
)
L
L
H
L
L
Data Out
Data Out
Read all bit
s
Active (I
CC
)
L
L
H
L
H
Data Out
High Z
Read lower bits only
Active (I
CC
)
L
L
H
H
L
High
Z
Data Out
Read upper bits only
Active (I
CC
)
L
X
L
L
L
Data In
Data In
Write all bits
Active (I
CC
)
L
X
L
L
H
Data In
High Z
Write lower bits only
Active (I
CC
)
L
X
L
H
L
High Z
Data In
Write upper bits only
Active (I
CC
)
L
H
H
X
X
High Z
High Z
Selec
ted, output
s disabled
Active (I
CC
)
CY7C101
1DV33
Document Number: 38-05609 Rev
. *H
Page 12 of 17
Ordering Code Definitions
Ordering Information
Spee
d
(ns)
Ordering Code
Package
Diagram
Package T
ype
Operating
Range
10
CY7C101
1DV33-10ZSXI
51-85087
44-
pin TSOP II (Pb-free)
Industrial
CY7C101
1DV33-10BVXI
51-85150
48-ball VFBGA (Pb-free)
Please contact your local Cypress sales representative for availability of these pa
rts
T
emperature Range:
I = Industrial
Pb-free
Package T
ype: XX = ZS or BV
ZS = 44-pin TSOP II
BV = 48-ball VFBGA
S
peed: 10 ns
V
oltage Range: V33 = 3 V to 3.6
V
Process T
echnology: D = C9, 90 nm T
echnology
Data Width: 1 = × 16-bits
Density: 01 = 2
-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
T
echnol
ogy Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
C
CY
1
V33
-
10
XX
7
01
1
D
I
X
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
CY7C1011DV33-10BVIT
Mfr. #:
Buy CY7C1011DV33-10BVIT
Manufacturer:
Cypress Semiconductor
Description:
SRAM 2M FAST ASYNC HI SPD SRAM IND
Lifecycle:
New from this manufacturer.
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