10
LTC1265/LTC1265-3.3/LTC1265-5
APPLICATIONS INFORMATION
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output voltage can potentially float above the maximum
allowable tolerance. To prevent this from occuring, a
resistor must be connected between V
OUT
and ground
with a value low enough to sink the maximum possible
leakage current.
THERMAL CONSIDERATIONS
In a majority of applications, the LTC1265 does not
dissipate much heat due to its high efficiency. However, in
applications where the switching regulator is running at
high duty cycles or the part is in dropout with the switch
turned on continuously (DC), the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated by the regulator
exceeds the maximum junction temperature of the part.
The temperature rise is given by:
T
R
= P(θ
JA
)
where P is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature is simply given by:
T
J
= T
R
+ T
A
As an example, consider the LTC1265 is in dropout at an
input voltage of 4V with a load current of 0.5A. From the
Typical Performance Characteristics graph of Switch Re-
sistance, the ON resistance of the P-channel is 0.55.
Therefore power dissipated by the part is:
P = I
2
(R
DSON
) = 0.1375W
For the SO package, the θ
JA
is 110°C/W.
Therefore the junction temperature of the regulator when
it is operating in ambient temperature of 25°C is:
T
J
= 0.1375(110) + 25 = 40.1°C
Remembering that the above junction temperature is
obtained from a R
DSON
at 25°C, we need to recalculate the
junction temperature based on a higher R
DSON
since it
increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Now consider the case of a 1A regulator with V
IN
= 4V and
T
A
= 65°C. Starting with the same 0.55 assumption for
R
DSON
, the T
J
calculation will yield 125°C. But from the
graph, this will increase the R
DSON
to 0.76, which when
used in the above calculation yields an actual T
J
> 148°C.
Therefore the LTC1265 would be unsuitable for a 4V input,
1A output regulator operating at T
A
= 65°C.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1265. These items are also illustrated graphically in
the layout diagram of Figure 6. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC1265 signal ground (Pin 11) must return to the (–)
plate of C
OUT
. The power ground (Pin 12) returns to the
anode of the Schottky diode, and the (–) plate of C
IN
,
whose leads should be as short as possible.
2. Does the (+) plate of the C
IN
connect to the power V
IN
(Pins 1,13) as close as possible? This capacitor pro-
vides the AC current to the internal P-channel MOSFET
and its driver.
3. Is the input decoupling capacitor (0.1µF) connected
closely between power V
IN
(Pins 1,13) and power
ground (Pin 12)? This capacitor carries the high fre-
quency peak currents.
4. Is the Schottky diode closely connected between the
power ground (Pin 12) and switch (Pin 14)?
5. Does the LTC1265 SENSE
(Pin 7) connect to a point
close to R
SENSE
and the (+) plate of C
OUT
? In adjustable
applications, the resistive divider, R1 and R2, must be
connected between the (+) plate of C
OUT
and signal
ground.
6. Are the SENSE
and SENSE
+
leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between Pins 7 and 8 should be as close as possible to
the LTC1265.
7. Is SHDN (Pin 10) actively pulled to ground during
normal operation? The SHDN pin is high impedance
and must not be allowed to float.
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LTC1265/LTC1265-3.3/LTC1265-5
Figure 7. C
T
Waveforms
Troubleshooting Hints
Since efficiency is critical to LTC1265 applications, it is
very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation. As
the LTC1265 is highly tolerant of poor layout, the output
voltage will still be regulated. Therefore, monitoring the
output voltage will not tell you whether you have a good or
bad layout. The waveform to monitor is the voltage on the
timing capacitor Pin 5.
In continuous mode the voltage on the C
T
pin is a sawtooth
with approximately 0.9V
P-P
swing. This voltage should
never dip below 2V as shown in Figure 7a.
When the load currents are low (I
LOAD
< I
BURST
) Burst
Mode operation occurs. The voltage on C
T
pin now falls to
ground for periods of time as shown in Figure 7b. During
this time the LTC1265 is in sleep mode with quiescent
current reduced to 160µA.
The inductor current should also be monitored. If the
circuit is poorly decoupled, the peak inductor current will
be haphazard as in Figure 8a. A well decoupled LTC1265
has a clean inductor current as in Figure 8b.
Figure 6. LTC1265 Layout Diagram (See Board Layout Checklist)
V
IN
V
IN
LB
OUT
LB
IN
C
T
I
TH
SENSE
1000pF
1000pF
LTC1265
SENSE
+
N/C (V
FB
)
SHDN
SGND
PGND
PWR V
IN
SW
14
13
12
11
10
9
8
C
IN
D1
0.1µF
C
OUT
R
SENSE
L
V
OUT
OUTPUT DIVIDER REQUIRED
WITH ADJUSTABLE VERSION ONLY
PWR V
IN
1k
3900pF
1
2
3
4
5
6
7
LTC1265 F06
SHDN
BOLD LINES INDICATE
HIGH PATH CURRENTS
R1
R2
+
+
3.3V
2.4V
0V
TIME
LTC1265 F07a
(a) CONTINUOUS MODE OPERATION
VOLTAGE AT C
T
(PIN 5)
3.3V
2.4V
0V
TIME
LTC1265 F07b
(b) Burst Mode OPERATION
VOLTAGE AT C
T
(PIN 5)
SLEEP MODE
APPLICATIO S I FOR ATIO
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LTC1265/LTC1265-3.3/LTC1265-5
22µH
0.125
V
OUT
3.3V
0.8A
C
OUT
1000pF
100pF
3900pF
1k
0.1µF
C
IN
D1
PWR V
IN
V
IN
SW
PGND
SENSE
+
SENSE
SGND
I
TH
C
T
LTC1265 F09
SHDN
LTC1265-3.3
V
IN
5V
+
+
Figure 9. Design Example Circuit
Figure 10. Design Example Efficiency Curve
LOAD CURRENT (mA)
0.01
70
EFFICIENCY (% )
75
80
85
90
100
0.1 1.0
1265 G11
95
L = DALE LPT4545-220 (22µH)
V
OUT
= 3.3V
C
T
= 100pF
Design Example
As a design example, assume V
IN
= 5V, V
OUT
= 3.3V, I
MAX
= 0.8A and f = 250kHz. With this information we can easily
calculate all the important components.
From (1),
R
SENSE
= 100mV/0.8 = 0.125
From (2) and assuming V
D
= 0.4V,
C
T
100pF
Using (3), the value of the inductor is:
L 5.2(10
5
)(0.125)(100pF)3.3V = 22µH
For the catch diode, a MBRS130LT3 or 1N5818 will be
sufficient in this application.
C
IN
will require an RMS current rating of at least 0.4A at
temperature, and C
OUT
will require an ESR of (from 5):
ESR
COUT
< 0.25
The inductor ripple current is given by:
I
RIPPLE
=
V
OUT
+ V
D
L
)
)
t
OFF
= 0.22A
At light loads the peak inductor current is at:
I
PEAK
= 25mV/0.125 = 0.2A
Therefore, at load current less than 0.1A the LTC1265 will
be in Burst Mode operation. Figure 9 shows the complete
circuit and Figure 10 shows the efficiency curve with the
above calculated component values.
(a) POORLY DECOUPLED LTC1265
(b) WELL DECOUPLED LTC1265
Figure 8. Inductor Waveforms
APPLICATIO S I FOR ATIO
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LTC1265CS-3.3#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Adj Hi Eff 1A Stepdn Converter
Lifecycle:
New from this manufacturer.
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