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2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
©
FEBRUARY 2009
CMOS SyncBiFIFO
TM
64 x 36 x 2
IDT723612
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
DSC-3136/3
FEATURES
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• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
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• Two independent clocked FIFOs (64 x 36 storage capacity
each) buffering data in opposite directions
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• Mailbox bypass Register for each FIFO
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• Programmable Almost-Full and Almost-Empty Flags
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• Microprocessor interface control logic
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• EFA, FFA, AEA, and AFA flags synchronized by CLKA
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• EFB, FFB, AEB, and AFB flags synchronized by CLKB
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• Passive parity checking on each port
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• Parity generation can be selected for each port
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Supports clock frequencies up to 67 MHz
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Fast access times of 10ns
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Available in 132-pin plastic quad flat package (PQF) or space-
saving 120-pin thin quad flat package (TQFP)
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Industrial temperature range (–40°C to +85°C) is available
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Green parts available, see ordering information
DESCRIPTION
The IDT723612 is a monolithic high-speed, low-power CMOS bi-directional
clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read
access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs
on board the chip buffer data in opposite directions. Each FIFO has flags to
indicate empty and full conditions and two programmable flags (Almost-Full and
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
3136 drw01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
Parity
Gen/Check
A
0
- A
35
36
RAM
ARRAY
64 x 36
Parity
Generation
Parity
Gen/Check
Programmable Flag
Offset Register
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
64 x 36
Parity
Generation
Read
Pointer
PEFB
PGB
EFB
AEB
FFB
AFB
ODD/
EVEN
FFA
AFA
FS0
FS1
EFA
AEA
PGA
PEFA
MBF2
Write
Pointer
FIFO2
FIFO1
36
36
B
0
- B
36
FUNCTIONAL BLOCK DIAGRAM