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IDT723612L20PF8

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1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
©
FEBRUARY 2009
CMOS SyncBiFIFO
TM
64 x 36 x 2
IDT723612
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
DSC-3136/3
FEATURES
••
••
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
••
••
• Two independent clocked FIFOs (64 x 36 storage capacity
each) buffering data in opposite directions
••
••
• Mailbox bypass Register for each FIFO
••
••
• Programmable Almost-Full and Almost-Empty Flags
••
••
• Microprocessor interface control logic
••
••
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
••
••
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
••
••
• Passive parity checking on each port
••
••
• Parity generation can be selected for each port
••
••
•
Supports clock frequencies up to 67 MHz
••
••
•
Fast access times of 10ns
••
••
•
Available in 132-pin plastic quad flat package (PQF) or space-
saving 120-pin thin quad flat package (TQFP)
••
••
•
Industrial temperature range (–40°C to +85°C) is available
••
••
•
Green parts available, see ordering information
DESCRIPTION
The IDT723612 is a monolithic high-speed, low-power CMOS bi-directional
clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read
access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs
on board the chip buffer data in opposite directions. Each FIFO has flags to
indicate empty and full conditions and two programmable flags (Almost-Full and
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
3136 drw01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
Parity
Gen/Check
A
0
- A
35
36
RAM
ARRAY
64 x 36
Parity
Generation
Parity
Gen/Check
Programmable Flag
Offset Register
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
64 x 36
Parity
Generation
Read
Pointer
PEFB
PGB
EFB
AEB
FFB
AFB
ODD/
EVEN
FFA
AFA
FS0
FS1
EFA
AEA
PGA
PEFA
MBF2
Write
Pointer
FIFO2
FIFO1
36
36
B
0
- B
36
FUNCTIONAL BLOCK DIAGRAM
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
NOTES:
1. Electrical pin 1 in center of beveled edge.
2. NC - No internal connection
3. Uses Yamaichi socket IC51-1324-828
PIN CONFIGURATIONS
GND
AEB
EFB
B
0
B1
B2
GND
B
3
B4
B5
B6
VCC
B7
B8
B9
GND
B
10
B11
VCC
B12
B13
B14
GND
B
15
B16
B17
B18
B19
B20
GND
B
21
B22
B23
117
17
16
15
14
13
12
11
10
9
8
7
6
4
3
2
1
132
130
129
128
127
126
125
124
123
122
121
120
119
118
131
5
GND
AEA
EFA
A
0
A1
A2
GND
A
3
A4
A5
A6
VCC
A7
A8
A9
GND
A
10
A11
VCC
A12
A13
A14
GND
A
15
A16
A17
A18
A19
A20
GND
A
21
A22
A23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3136 drw02
VCC
VCC
A24
A25
A26
A27
GND
A
28
A29
VCC
A30
A31
A32
GND
A33
A34
A35
GND
B
35
B34
B33
GND
B
32
B31
B30
VCC
B29
B28
B27
GND
B
26
B25
B24
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
AFB
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
FS
0
ODD/EVEN
FS
1
PEFA
MBF2
RST
NC
GND
NC
NC
NC
MBF1
GND
PEFB
V
CC
W/RB
CLKB
ENB
CSB
FFB
GND
MBA
MBB
PGB
PQFP
(2)
(PQ132-1, ORDER CODE: PQF)
TOP VIEW
Almost-Empty) to indicate when a selected number of words is stored in
memory. Communication between each port can bypass the FIFOs via two
36-bit mailbox registers. Each mailbox register has a flag to signal when new
mail has been stored. Parity is checked passively on each port and may be
ignored if not desired. Parity generation can be selected for data read from
each port. Two or more devices can be used in parallel to create wider data
paths.
This device is a clocked FIFO, which means each port employs a synchronous
interface. All data transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bi-directional interface
between microprocessors and/or buses with synchronous control.
The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are
two-stage synchronized to the port clock that writes data to its array. The Empty
Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
The IDT723612 is characterized for operation from 0°C to 70°C.
3
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
PIN CONFIGURATIONS (CONTINUED)
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
NOTES:
1. Pin 1 identifier in corner.
2. NC - No internal connection
B22
B21
GND
B
20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B
9
B8
B7
VCC
B6
B5
B4
B3
GND
B
2
B1
B0
EFB
AEB
AFB
A23
A22
A21
GND
A
20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A
9
A8
A7
VCC
A6
A5
A4
A3
GND
A
2
A1
A0
EFA
AEA
3136 drw03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF
2
MBA
FS
1
FS0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF
1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
FFB
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
B
23
A24
A25
A26
VCC
A27
A28
A29
GND
A
30
A31
A34
A35
B35
GND
B
34
B33
B32
B30
B31
GND
B
29
B28
B27
VCC
B26
B25
B24
A32
A33
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IDT723612L20PF8

Mfr. #:
Buy IDT723612L20PF8
Manufacturer:
Description:
IC FIFO 64X36X2 20NS 120QFP
Lifecycle:
New from this manufacturer.
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