MAX1106/MAX1107
Single-Supply, Low-Power,
Serial 8-Bit ADCs
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where R
IN
= 6.5kΩ, R
S
= the source impedance of the
input signal, and t
ACQ
must never be less than 1µs.
This is easily achieved by respecting the minimum
CONVST high interval required and the time required to
clock the data out.
Pseudo-Differential Input
The MAX1106/MAX1107 input configuration is pseudo-
differential to the extent that only the signal at the sam-
pled input (IN+) is stored in the holding capacitor
(C
HOLD
). IN- must remain stable within ±0.5LSB
(±0.1LSB for best results) in relation to GND during a
conversion.
If a varying signal is applied at the IN- input, its ampli-
tude and frequency need to be limited. The following
equations determine the relationship between the maxi-
mum signal amplitude and its frequency to maintain
±0.5LSB accuracy:
Assuming a sinusoidal signal at the IN- input,
under the maximum voltage variation is determined by
a 60Hz signal at IN- with an amplitude of 1.2V will
generate ±0.5LSB of error. This is with a 35µs conver-
sion time (maximum t
CONV
) and a reference voltage of
4.096V. When a DC reference voltage is used at IN-,
connect a 0.1µF capacitor from IN_ to GND to minimize
noise at the input.
The common-mode input range of IN+ and IN- is GND
to +V
DD
. Full-scale is achieved when (V
IN-
- V
IN+
) =
V
REFIN
. V
IN+
must be higher than V
IN-
.
Conversion Process
The comparator negative input is connected to the auto-
zero rail. Since the device requires only a single supply,
the ZERO node at the input of the comparator equals
V
DD
/2. The capacitive DAC restores node ZERO to have
0V difference at the comparator inputs within the limits
of 8-bit resolution. This action is equivalent to transfer-
ring a charge of 18pF(V
IN+
- V
IN-
) from C
HOLD
to the
binary-weighted capacitive DAC which, in turn, forms a
digital representation of the analog-input signal.
Input Voltage Range
Internal protection diodes that clamp the analog input to
V
DD
and GND allow the input pins (IN+ and IN-) to swing
from (GND - 0.3V) to (V
DD
+ 0.3V) without damage.
However, for accurate conversions, the inputs must not
exceed (V
DD
+ 50mV) or be less than (GND - 50mV).
The MAX1106/MAX1107 input range is from GND to
V
DD
. The output code is invalid (code zero) when a
negative input voltage (or a negative differential input
voltage) is applied. The reference input-voltage range
at REFIN is from 1V to (V
DD
+ 50mV).
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Serial Interface
The MAX1106/MAX1107 have a 3-wire serial interface.
The CONVST and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the result of conversion.
The serial interface provides easy connection to micro-
controllers with SPI, QSPI, and MICROWIRE serial inter-
faces at clock rates up to 2MHz. For SPI and QSPI, set
CPOL = CPHA = 0 in the SPI control registers of the
microcontroller. Figure 5 shows the MAX1106/MAX1107
common serial-interface connections.
Digital Inputs and Outputs
The logic levels of the MAX1106/MAX1107 digital
inputs are set to accept voltage levels from both 3V
and 5V systems regardless of the supply voltages.
A conversion is started by toggling CONVST. CONVST
idles low and needs to be set high for at least 1µs to
perform the autozero adjustment. CONVST must remain
low during conversion and until the result of conversion
has been clocked out.
After CONVST is set low, allow 35µs for the conversion
to be completed. While the internal conversion is in
progress DOUT is low. Conversion is controlled by an
internal 400kHz oscillator. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 9). Data is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 2MHz. Once all data bits are clocked out,
DOUT goes high impedance at the falling edge of the
eighth SCLK pulse.
