AT89C1051U
3
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 1
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to
P1.7 provide internal pullups. P1.0 and P1.1 require exter-
nal pullups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the
on-chip precision analog comparator. The Port 1 output
buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as
inputs. When pins P1.2 to P1.7 are used as inputs and are
externally pulled low, they will source current (I
IL
) because
of the internal pullups.
Port 1 also receives code data during Flash programming
and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O
pins with internal pullups. P3.6 is hard-wired as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (I
IL
) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C1051U as listed below:
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine
cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Figure 1. Oscillator Connections
Note: C1, C2= 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
(external interrupt 0)
P3.3 INT1
(external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
