MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
_______________________________________________________________________________________ 7
Detailed Description
The MAX9311/MAX9313 are low skew, 1-to-10 differen-
tial drivers designed for clock and data distribution.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLKSEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLKSEL is set by an
internal V
BB
voltage reference. The CLKSEL input can
be driven to V
CC
and V
EE
or by a single-ended LVPECL/
LVECL signal. The selected input is reproduced at 10
differential outputs.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribu-
tion in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
The differential inputs can be configured to accept sin-
gle-ended inputs when operating at approximately V
CC
-
V
EE
= +3.0V to +3.8V for the MAX9311 or V
CC
- V
EE
=
+2.7V to +3.8V for the MAX9313. This is accomplished
by connecting the on-chip reference voltage, V
BB
, to an
input as a reference. For example, the differential CLK0,
CLK0 input is converted to a noninverting, single-ended
input by connecting V
BB
to CLK0 and connecting the
single-ended input to CLK0. Similarly, an inverting input
is obtained by connecting V
BB
to CLK0 and connecting
the single-ended input to CLK0. With a differential input
configured as single-ended (using V
BB
), the single-
ended input can be driven to V
CC
and V
EE
or with a sin-
gle-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using V
BB
), the approximate supply range is V
CC
-
V
EE
= +3.0V to +3.8V for the MAX9311 and V
CC
- V
EE
=
+2.7V to +3.8V for the MAX9313. This is because one of
the inputs must be V
EE
+ 1.2V or higher for proper oper-
ation of the input stage. V
BB
must be at least V
EE
+ 1.2V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
mum V
BB
= V
EE
+ 1.2V.
The minimum V
BB
output for the MAX9311 is V
CC
-
1.525V and the minimum V
BB
output for the MAX9313 is
V
CC
- 1.38V. Substituting the minimum V
BB
output for
each device into V
BB
= V
EE
+ 1.2V results in a minimum
supply of 2.725V for the MAX9311 and 2.58V for the
MAX9313. Rounding up to standard supplies gives the
single-ended operating supply ranges of V
CC
- V
EE
=
3.0V to 3.8V for the MAX9311 and V
CC
- V
EE
= 2.7V to
3.8V for the MAX9313.
When using the V
BB
reference output, bypass it with a
0.01µF ceramic capacitor to V
CC
. If the V
BB
reference is
not used, it can be left open. The V
BB
reference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use V
BB
only for inputs that are on the same
device as the V
BB
reference.
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or V
CC
- V
EE
, whichever is less.
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLK0 and CLK1) are biased with a
75k pullup to V
CC
and a 75k pulldown to V
EE
. The
noninverting inputs (CLK0 and CLK1) are biased with a
75k pulldown to V
EE
. The single-ended CLKSEL input
does not have a bias resistor. If not driven, pull CLKSEL
up or down with a 1kHz resistor (see Pin Description).
Specifications for the high and low voltages of a differen-
tial input (V
IHD
and V
ILD
) and the differential input volt-
age (V
IHD
- V
ILD
) apply simultaneously (V
ILD
cannot be
higher than V
IHD
).
Output levels are referenced to V
CC
and are considered
LVPECL or LVECL, depending on the level of the V
CC
supply. With V
CC
connected to a positive supply and
V
EE
connected to GND, the outputs are LVPECL. The
outputs are LVECL when V
CC
is connected to GND and
V
EE
is connected to a negative supply.
A single-ended input of at least V
BB
±95mV or a differen-
tial input of at least 95mV switches the outputs to the
V
OH
and V
OL
levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as close
to the device as possible, with the 0.01µF value capaci-
tor closest to the device. Use multiple parallel vias for
low inductance. When using the V
BB
reference output,
bypass it with a 0.01µF ceramic capacitor to V
CC
(if the
V
BB
reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9311/MAX9313. Connect each signal
of a differential input or output to a 50 characteristic
impedance trace. Minimize the number of vias to prevent
impedance discontinuities. Reduce reflections by main-
taining the 50 characteristic impedance through con-
nectors and across cables. Reduce skew within a
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
8 _______________________________________________________________________________________
differential pair by matching the electrical length of the
traces.
Output Termination
Terminate outputs through 50 to V
CC
- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 250
V
IL
V
IH
V
OH
-
V
OL
V
OH
V
OL
Q_
Q_
CLK_
CLK_
(CONNECTED TO CLK_)
V
BB
Figure 1. Switching with Single-Ended Input
0 (DIFFERENTIAL)
80%
20%
80%
20%
0 (DIFFERENTIAL)
V
OH
- V
OL
V
IHD
- V
ILD
V
IHD
V
ILD
Q_
Q_
(Q_) - (Q_)
CLK_
CLK_
t
PLHD
t
PHLD
t
R
t
F
V
OH
V
OL
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
_______________________________________________________________________________________ 9
Q0
CLK0
0
1
V
CC
75k
75k 75k
Q0
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q1
Q1
CLK0
CLK1
CLKSEL
V
CC
75k
75k 75k
CLK1
V
EE
V
EE
V
EE
V
EE
V
BB
Functional Diagram

MAX9311ECJ+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Clock Drivers & Distribution LVPECL/LVECL/HSTL Clock & Data Driver
Lifecycle:
New from this manufacturer.
Delivery:
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