7©2016 Integrated Device Technology, Inc Revision A February 9, 2016
8S89875I Data Sheet
Parameter Measurement Information
LVDS Output Load AC Test Circuit
Part-to-Part Skew
Additive Cycle-to-Cycle Jitter, RMS
Output Skew
Propagation Delay
Output Rise/Fall Time
tsk(pp)
Part 1
Part 2
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
Additive tjit(cc) = tjit(cc)_output
2
tjit(cc)_input
2
Qx
nQx
Qy
nQy
t
PD
nQ0, nQ1
Q0, Q1
nIN
IN
20%
80%
80%
20%
t
R
t
F
V
OD
nQ0, nQ1
Q0, Q1
8©2016 Integrated Device Technology, Inc Revision A February 9, 2016
8S89875I Data Sheet
Parameter Measurement Information, continued
Single-Ended & Differential Input Voltage Swing
Offset Voltage Setup
Differential Output Voltage Setup
V
IN
, V
OUT
V
DIFF_IN
Differential Voltage Swing = 2 x Single-ended V
IN
out
out
LVDS
DC Input
V
OCM
/
Δ
V
OCM
V
DD
100
out
out
LVDS
DC Input
V
OUT
V
DD
9©2016 Integrated Device Technology, Inc Revision A February 9, 2016
8S89875I Data Sheet
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, we recommend that there
is no trace attached.
2.5V LVPECL Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both signals must meet the V
IN
and V
IH
input requirements. Figures 2A to 2D show interface
examples for the IN /nIN with built-in 50 termination input driven by
the most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 2A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 2C. IN/nIN Input with Built-In 50
Driven by a CML Driver
Figure 2B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure 2D. IN/nIN Input with Built-In 50
Driven by a CML Driver with Built-In 50
Pullup

8S89875AKILF

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution SMALL SIGE ARRAY
Lifecycle:
New from this manufacturer.
Delivery:
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