NCP5203
http://onsemi.com
7
DETAILED OPERATING DESCRIPTION
General
The NCP5203 2−in−1 DDR Power Controller combines
the efficiency of a VDDQ PWM controller with the
simplicity of a linear regulator for VTT termination. Both
VDDQ and VTT outputs can be user adjusted.
The inclusion of both VDDQ and VTT power good
voltage monitors, soft−start, VDDQ overvoltage and
undervoltage detection, supply undervoltage monitors, and
thermal shutdown, makes this device a total power solution
for high current DDR memory systems.
VDDQ Switching Regulator in Normal (S0) Mode
The VDDQ regulator is a switching synchronous
rectification buck controller directly driving two external
N−Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM (300 kHz ± 12.5%)
with external compensation. The VDDQ output voltage is
divided down and fed back to the inverting input of an
internal amplifier through the FBDDQ pin to close the loop
at VDDQ = VFBDDQ × (1 + R2/R1). This amplifier
compares the feedback voltage with an internal VREF1
(= 1.25 V) to generate an error signal for the PWM
comparator. This error signal is further compared with a
fixed frequency Ramp waveform derived from the internal
oscillator to generate a pulse−width−modulated signal.
This PWM signal drives the external N−Channel Power
FETs via the TGDDQ and BGDDQ pins. External inductor
L and capacitor COUT1 filter the output. The VDDQ
output voltage ramps up at a pre−defined soft−start rate
each time the IC exits S5. When in normal mode, and
regulation of VDDQ is detected, signal INREGDDQ will
go high to notify the control logic block.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive non−overlap timing control of the
complementary gate drive output signals is provided to
reduce shoot−through current.
Tolerance of VDDQ
The tolerance of VFBDDQ and the ratio of the external
resistor divider R2/R1 both impact the precision of VDDQ.
When the control loop is in regulation, VDDQ = VFBDDQ
× (1 + R2/R1). With a worst case (overtemperature)
VFBDDQ tolerance of ±2%, a worst case range of 2.5% for
VDDQ will be assured if the ratio R2/R1 is specified as
0.98985 ±1%.
Table 1. State, Operation, Input and Output Condition Table
USER INPUTS OPERATING CONDITIONS OUTPUT CONDITIONS
MODE
5VDUAL
UVLO
VDDQEN VTTEN VDDQ VTT TGDDQ BGDDQ PGOOD
S5 Low X X H−Z H−Z Low Low Low
S0 High High High Normal Normal Normal
(300 kHz)
Normal
(300 kHz)
H−Z
S3 High High Low Standby H−Z Normal
(600 kHz)
Low Low
S5 High Low X H−Z H−Z Low Low Low
VDDQ Regulator in Standby Mode (S3)
During S3, the VDDQ regulator operates in
asynchronous switch mode. The switching frequency is
increased to 600 kHz, the low−side FET is disabled, and the
body diode of the low side FET is used. The regulator will
operate in discontinuous conduction mode (DCM) and the
switching frequency is doubled to reduce peak conduction
current.
VDDQ Regulator Fault Protection
During S0 and S3, the external resistor (RL1) sets the
current limit for the high−side switch. An internal 35 A
current sink at OCDDQ pin establishes a voltage drop
across this resistor. This voltage is compared to the voltage
at SWDDQ pin when the TGDDQ is high after a fixed
blanking period of 500 ns to avoid false current limit
triggering. When the voltage at SWDDQ is lower than
OCDDQ, an overcurrent condition occurs, upon which all
outputs will be latched off to protect against a
short−to−ground condition on SWDDQ or VDDQ. The IC
will be reset once 5VDUAL or VDDQEN is cycled.
VDDQ Regulator Feedback Compensation
The recommended compensation network is shown in
Figure 2.
