8
EM681FV16B Family
Low Power, 512Kx16 SRAM
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting
UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest
transition when CS
goes high and WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as CS or WE going high.
AUGUST 2010
512K X 16 BIT LOW POWER CMOS SRAM
AS6C8016A
t
WC
Address
CS
UB,LB
WE
Data in
Data out
t
CW
(2)
t
WR
(4)
t
BW
t
WP
(1)
t
DW
t
DH
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
High-Z High-Z
Data Valid
t
AS
(3)
t
AW
