Building an EZ-Host/OTG Project From Start to Finish
4
Source Code
BAL.c
#include "cy7c67200_300.h"
typedef unsigned short uint16;
#define WRITE_REGISTER(address, value) (*(volatile uint16 *) (address)) = ( (uint16) (value) )
#define READ_REGISTER(address) (*(volatile uint16 *) (address))
#define INPLACE_OR(address, value) __asm( "or [%0], %1" : : "p" ((address)), "g" ((value)) )
#define INPLACE_AND(address, value) __asm( "and [%0], %1" : : "p" ((address)), "g" ((value)) )
void writeCPLDADX(uint16 address)
{
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0008); /* A0 = 0 */
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0020); /* nCS = 0 */
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0040); /* nWR = 0 */
INPLACE_OR(GPIO0_DIR_REG, 0x00FF); /*Write Address*/
WRITE_REGISTER(GPIO0_OUT_DATA_REG, address);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0040); /* nWR = 1 */
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0020); /* nCS = 1 */
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008); /* A0 = 1 */
}
void writeCPLDDATA(uint16 data)
{
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008); /* A0 = 1 */
INPLACE_AND(GPIO1_OUT_DATA_REG,~0x0020); /* nCS = 0 */
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0040); /* nWR = 0 */
INPLACE_OR(GPIO0_DIR_REG, 0x00FF); /*Write Address*/
WRITE_REGISTER(GPIO0_OUT_DATA_REG, data);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0040); /* nWR = 1 */
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0020); /* nCS = 1 */
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008); /* A0 = 1 */
}
int readCPLDDATA()
{
uint16 data;
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008); /* A0 = 1 */
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0020); /* nCS = 0 */
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0080); /* nRD = 0 */
INPLACE_AND(GPIO0_DIR_REG, 0xFF00); /*Write Address*/
data = (READ_REGISTER(GPIO0_IN_DATA_REG) & 0x00FF);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0080); /* nWR = 1 */
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0020); /* nCS = 1 */
return data;
}
void writeCPLD(int address, int data)
{
writeCPLDADX(address);
writeCPLDDATA(data);
}
int readCPLD(int address)
{
writeCPLDADX(address);
return readCPLDDATA();
}
int main()
{
uint16 button_read = 0;
INPLACE_AND(UART_CTL_REG, 0xFE); /* Disable UART to free up GPIO 6 & 7 on EZ-OTG for CPLD*/
INPLACE_OR(GPIO0_OUT_DATA_REG, 0x00FF); /* Data Port */
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x00E8); /* A0 = nCS = nRD = nWR = 1 */
INPLACE_OR(GPIO0_DIR_REG, 0x00FF);
INPLACE_OR(GPIO1_DIR_REG, 0x00FF);