MAX1391/MAX1394
4 _______________________________________________________________________________________
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.5V to +3.6V, V
REF
= V
DD
, C
REF
= 0.1µF, f
SCLK
= 5MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
DD
= 1.6V 125 150
f
SAMPLE
= 100ksps
V
DD
= 3V 150 200
V
DD
= 1.6V 520 600
f
SAMPLE
= 416ksps
V
DD
= 3V 710 800
Power-down mode (Note 5) 5 10
Positive Supply Current (Note 4) I
DD
Power-down mode (Note 6) 0.2 ±2.5
µA
Power-Supply Rejection PSR V
DD
= 1.6V to 3.6V, full-scale input (Note 7) ±150 ±1000 µV/V
TIMING CHARACTERISTICS
(V
DD
= +1.5V to +3.6V, V
REF
= V
DD
, C
REF
= 0.1µF, f
SCLK
= 5MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Figure 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
200 10,000 ns
SCLK Pulse-Width High t
CH
90 ns
SCLK Pulse-Width Low t
CL
90 ns
CS Fall to SCLK Rise Setup t
CSS
80 ns
SCLK Rise to CS Fall Ignore t
CSO
0ns
SCLK Fall to DOUT Valid t
DOV
C
LOAD
= 0 to 30pF 10 80 ns
OE Rise to DOUT Disable t
DOD
620ns
OE Fall to DOUT Enable t
DOE
920ns
CS Pulse-Width High and Low t
CSW
80 ns
OE Pulse-Width High and Low t
OEW
80 ns
CH1/CH2 Setup Time (to the First
SCLK)
t
CHS
MAX1394 only 10 ns
CH1/CH2 Hold Time (to the First
SCLK)
t
CHH
MAX1394 only 0 ns
UNI/BIP Setup Time (to the First
SCLK)
t
UBS
MAX1391 only 10 ns
UNI/BIP Hold Time (to the First
SCLK)
t
UBH
MAX1391 only 0 ns
Note 1: Devices are production tested at room and +85°C. Specification to -40°C are guaranteed by design.
Note 2: V
DD
= 1.6V, V
REF
= 1.6V, and V
AIN
= 1.6V.
Note 3: V
DD
= 1.6V, V
REF
= 1.6V, V
AIN
= 1.6V
P-P
, f
SCLK
= 5MHz, f
SAMPLE
= 416ksps, and f
IN
(sine wave) = 100kHz.
Note 4: All digital inputs swing between V
DD
and GND. V
REF
= V
DD
, f
IN
= 100kHz sine wave, V
AIN
= V
REFP-P,
C
LOAD
= 30pF on DOUT.
Note 5: CS = V
DD
, OE = UNI/BIP = CH1/CH2 = V
DD
or GND, SCLK is active.
Note 6: CS = V
DD
, OE = UNI/BIP = CH1/CH2 = V
DD
or GND, SCLK is inactive.
Note 7: Change in V
AIN
at code boundary 254.5.
