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NB7L1008MNG

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 1
1 Publication Order Number:
NB7L1008/D
NB7L1008
2.5V / 3.3V 1:8 LVPECL
Fanout Buffer
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L1008 is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008 produces eight identical output copies
of Clock or Data operating up to 7 GHz or 12 Gb/s, respectively. As
such, the NB7L1008 is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pin. This feature allows the NB7L1008 to
accept various logic standards, such as LVPECL, CML, LVDS logic
levels. The V
REFAC
reference output can be used to rebias
capacitor−coupled differential or single−ended input signals. The 1:8
fanout design was optimized for low output skew applications. The
NB7L1008 is a member of the GigaComm™ family of high
performance clock products.
Features
• Typical Maximum Input Data Rate > 12 Gb/s Typical
• Data Dependent Jitter < 15 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:8 LVPECL Outputs, < 20 ps max
• Multi−Level Inputs, accepts LVPECL, CML, LVDS
• 160 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
• Operating Range: V
CC
= 2.375 V to 3.6 V, GND = 0 V
• Internal Input Termination Resistors, 50 W
• V
REFAC
Reference Output
• QFN−32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free and Halide−Free Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 9 o
f
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
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32
1
NB7L
1008
AWLYYWWG
G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
SIMPLIFIED LOGIC DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
V
REFAC
IN
VT
IN
Q6
Q6
Q7
Q7
32
(Note: Microdot may be in either location)
50W
50W
NB7L1008
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2
VCC
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
VCC
VREFAC
VCC
GND
VCC
Q4
Q4
Q3
Q3
GND
VCC
IN
VT
IN
GND
GND
Figure 1. 32−Lead QFN Pinout (Top View)
NB7L1008
Exposed Pad
(EP)
Q7
Q7
Q6
Q6
Q5
Q5
VCC
VCC
Q0
Q0
Q1
Q1
Q2
Q2
VCC
Table 1. PIN DESCRIPTION
Pin Name I/O Description
3, 6 IN, IN LVPECL, CML,
LVDS Input
Non−inverted / Inverted Differential Clock/Data Input. Note 1
4 VT
Internal 50 W Termination Pin for IN and IN
2, 7 17,24 GND Negative Supply Voltage, Note 2
1, 8, 9, 16, 18,
23, 25, 32
V
CC
Positive Supply Voltage, Note 2
31, 30, 29, 28,
27, 26, 22, 21,
20, 19, 15, 14,
13, 12, 11, 10
Q0, Q0, Q1,
Q1
, Q2, Q2,
Q3, Q3
, Q4,
Q4
, Q5, Q5,
Q6, Q6, Q7, Q7
LVPECL Non−inverted / Inverted Differential Output.
5 VREFAC Output Voltage Reference for Capacitor−Coupled Inputs, only
− EP − The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat−sinking conduit. The pad is electrically connected to GND and is
recommended to be electrically connected to GND on the PC board.
1. In the differential configuration when the input termination pin (V
T
) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN
, then the device will be susceptible to self−oscillation.
2. All V
CC
and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
NB7L1008
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3
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity (Note 3) Indefinite Time of the Drypack
QFN−32
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 263
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, refer to Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 4.0 V
V
IN
Input Voltage GND = 0 V −0.5 to V
CC
V
V
INPP
Differential Input Voltage |IN − IN| 1.89 V
I
IN
Input Current Through R
T
(50 W Resistor)
$40 mA
I
out
Output Current Continuous
Surge
34
40
mA
I
VFREFAC
V
REFAC
Sink/Source Current $1.5 mA
T
A
Operating Temperature Range −40 to +85
°C
T
stg
Storage Temperature Range −65 to +150
°C
q
JA
Thermal Resistance (Junction−to−Ambient) (Note 4)
TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias
500 lfpm QFN−32 27
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard
Board
QFN−32 12
°C/W
T
sol
Wave Solder Pb−Free 265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
P1-P3P4-P6P7-P9P10-P10

NB7L1008MNG

Mfr. #:
Buy NB7L1008MNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V / 3.3V 1:8 PECL FANO
Lifecycle:
New from this manufacturer.
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