LT3682
7
3682f
TEMPERATURE(°C)
50
3682 G28
90
85
80
70
25
0
25 50 100 12575
95
THRESTHOLD VOLTAGE (%)
5µs/DIV
V
OUT
20mV/DIV
I
L
0.2A/DIV
V
SW
5V/DIV
3682 G29
V
IN
= 12V; FRONT PAGE APPLICATION
I
LOAD
= 5mA
1µs/DIV
V
OUT
20mV/DIV
I
L
0.2A/DIV
V
SW
5V/DIV
3682 G30
V
IN
= 12V; FRONT PAGE APPLICATION
I
LOAD
= 55mA
1µs/DIV
V
OUT
20mV/DIV
I
L
0.5A/DIV
V
SW
5V/DIV
3682 G31
V
IN
= 12V; FRONT PAGE APPLICATION
I
LOAD
= 500mA
Switching Waveforms; Burst Mode
Switching Waveforms; Transition
from Burst Mode to Full Frequency
Switching Waveforms; Full
Frequency Continuous Operation
Power Good Threshold
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, unless otherwise noted.
LT3682
8
3682f
PIN FUNCTIONS
V
C
(Pin 1): The V
C
pin is the output of the internal error
amplifi er. The voltage on this pin controls the peak switch
current. Tie an RC network from this pin to ground to
compensate the control loop.
FB (Pin 2): The LT3682 regulates the FB pin to 0.8V. Connect
the feedback resistor divider tap to this pin.
PG (Pin 3): The PG pin is the open collector output of an
internal comparator. PG remains low until the FB pin is
within 10% of the fi nal regulation voltage. PG output is
valid when V
IN
is above the minimum input voltage and
RUN/SS is high.
GND (Pin 4): The GND pin is the ground of all the internal
circuitry. Tie directly to the local GND plane.
BD (Pin 5): This pin connects to the anode of the boost
Schottky diode. BD also supplies current to the LT3682’s
internal regulator.
BOOST (Pin 6): This pin is used to provide a drive volt-
age, higher than the input voltage, to the internal bipolar
NPN power switch. Connect a capacitor (typically 0.22µF)
between BOOST and SW.
DA (Pin 7): Connect the anode of the catch diode (D1
in Block Diagram) to this pin. Internal circuitry senses
the current through the catch diode providing frequency
foldback in extreme situations.
SW (Pin 8): The SW pin is the output of the internal power
switch. Connect this pin to the inductor, catch diode and
boost capacitor.
RUN/SS (Pin 9): The RUN/SS pin is used to put the LT3682
in shutdown mode. Tie to ground to shut down the LT3682.
Tie to 2.5V or more for normal operation. RUN/SS also
provides a soft-start function; see the Applications Infor-
mation section for more information.
R
T
(Pin 10): Oscillator Resistor Input. Connect a resistor
from this pin to ground to set the switching frequency.
SYNC (Pin 11): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to 0.8V or more for pulse skipping
mode operation. Tie to a clock source for synchronization.
Clock edges should have rise and fall times faster than
1µs. Note that the maximum load current depends on
which mode is chosen. See the Applications Information
section for more information.
V
IN
(Pin 12): The V
IN
pin supplies current to the LT3682’s
internal regulator and to the internal power switch. This
pin must be locally bypassed.
Exposed Pad (Pin 13): PGND. This is the power ground used
by the catch diode (D1) when its anode is connected to the
DA pin. The exposed pad must be soldered to the PCB.
LT3682
9
3682f
BLOCK DIAGRAM
V
IN
V
IN
V
OUT
C1
R
T
PG
RUN/SS
SYNC
R
T
+
INTERNAL 0.8V REF
2
+
SOFT START
0.720V
ERROR AMP
OSCILLATOR
250kHz-2.2MHz
DISABLE
SYNC
OUT
OUTB
+
+
BURST MODE
DETECT
THERMAL
SHUTDOWN
VC CLAMP
7
8
5
6
1
9
11
3
12
10
R1R2
FBGND
OVLO
SLOPE COMP
R
S
Q
DA
PGND
SW
BOOST
BD
V
C
C
C
C3
L1
D1
C2
C
F
R
C
3682 BD
13
4

LT3682IDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1A uP Buck Sw Reg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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