MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER
IDT™
16 OUTPUT LOW SKEW CLOCK GENERATOR 3
MK74CG117B REV E 122209
Pin Descriptions
External Components
The MK74CG117B requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.1µF must be connected
between each VDD and GND. Connect the capacitor as
close to these pins as possible. For optimum device
performance, mount the decoupling capacitor on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, observe the following guidelines:
1) Mount the 0.01µF decoupling capacitor on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to the VDD pin and
the PCB trace to the ground via should be kept as short as
possible.
2) To minimize EMI, place the 33Ω series-termination
resistor (if needed) close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through other
signal layers. Other signal traces should be routed away
from the MK74CG117B device. This includes signal traces
located underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant crystal. The oscillator has
internal caps that provide the proper load for a crystal with
C
L
= 18 pF. The value of these capacitors is given by the
following equation:
Crystal caps (pF) = (C
L
- 18) x 2
Pin
Number
Pin
Name
Pin Type Pin Description
1, 15, 16, 24, 30, 35, 36, 45, 46 VDD Power Connect to VDD.
2 X1/ICLK XI Connect to a crystal input or clock.
3 X2 XO Connect to a crystal, or leave unconnected for clock
input.
4, 5, 21, 29, 44 NC — No connect. Nothing is connected to these pins.
6, 7, 11, 12, 19, 20, 27, 28, 40, 41 GND Power Connect to ground.
8, 10, 48 S2, S1, S0 Input Multiplier select pins. See table 2.
9 REF Output Crystal oscillator buffered reference clock output.
13, 14, 17, 18 CLK1 - 4 Output Clock 1 - 4. Can be either full or half speed per Table
1.
22, 23, 25, 26, 31, 32, 33, 37 CLK5 - 12 Output Clock outputs 5 - 12. At full (1x) speed unless
tristated per Table 1.
34, 39 M0, M1 Input Mode Select pins. Selects tri-state or speed of
outputs per Table 1.
38, 42, 43, 47 CLK13 - 16 Output Clock 13 - 16. Can be either full or half speed per
Table 1.
