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551SDCGI8

P1-P3P4-P6P7-P9P10-P12
LOW SKEW 1 TO 4 CLOCK BUFFER 4 REVISION A 03/18/15
551S DATASHEET
DC Electrical Characteristics
VDD=1.8 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2.
VDD=2.5 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2.
VDD=3.3 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2.
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 1.71 1.89 V
Input High Voltage, ICLK V
IH
Note 1 0.7xVDD 1.89 V
Input Low Voltage, ICLK V
IL
Note 1 0.3xVDD V
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -10 mA 1.3 V
Output Low Voltage V
OL
I
OL
= 10 mA 0.35 V
Operating Supply Current IDD No load, 135 MHz 13 mA
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
OE pin 5 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 2.375 2.625 V
Input High Voltage, ICLK V
IH
Note 1 0.7xVDD 2.625 V
Input Low Voltage, ICLK V
IL
Note 1 0.3xVDD V
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -16 mA 1.8 V
Output Low Voltage V
OL
I
OL
= 16 mA 0.5 V
Operating Supply Current IDD No load, 135 MHz 18 mA
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
OE pin 5 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.135 3.465 V
Input High Voltage, ICLK V
IH
Note 1 0.7xVDD 3.465 V
Input Low Voltage, ICLK V
IL
Note 1 0.3xVDD V
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -25 mA 2.2 V
Output Low Voltage V
OL
I
OL
= 25 mA 0.7 V
Operating Supply Current IDD No load, 135 MHz 22 mA
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
OE pin 5 pF
REVISION A 03/18/15 5 LOW SKEW 1 TO 4 CLOCK BUFFER
551S DATASHEET
AC Electrical Characteristics
VDD=1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
VDD=2.5V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
VDD=3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
4. With external series resistor of 33 positioned close to each output pin.
Parameter Symbol Conditions Min. Typ. Max. Units
Output Frequency 5pF load, Note 4 200 MHz
Output Clock Rise Time t
OR
0.36 to 1.44 V 0.6 1.0 ns
Output Clock Fall Time t
OF
1.44 to 0.36V 0.6 1.0 ns
Propagation Delay 135 MHz, Note 1 1.5 2 4 ns
Buffer Additive Phase Jitter, RMS 125MHz, Integration range: 12kHz–20MHz 0.03 0.05 ps
Output to Output Skew Rising edges at VDD/2, Note 2 50 65 ps
Start-up Time t
START-UP
Part start-up time for valid outputs after VDD
ramp-up
2ms
Output Enable Time t
EN
CL < 5pF 3 cycles
Output Disable Time t
DIS
CL < 5pF 3 cycles
Parameter Symbol Conditions Min. Typ. Max. Units
Output Frequency 5pF load, Note 4 200 MHz
Output Clock Rise Time t
OR
0.5 to 2.0V 0.6 1.0 ns
Output Clock Fall Time t
OF
2.0 to 0.5V 0.6 1.0 ns
Propagation Delay 135 MHz, Note 1 1.8 2.5 4.5 ns
Buffer Additive Phase Jitter, RMS 125MHz, Integration range: 12kHz–20MHz 0.035 0.05 ps
Output to Output Skew Rising edges at VDD/2, Note 2 50 65 ps
Start-up Time t
START-UP
Part start-up time for valid outputs after VDD
ramp-up
2ms
Output Enable Time t
EN
CL < 5pF 3 cycles
Output Disable Time t
DIS
CL < 5pF 3 cycles
Parameter Symbol Conditions Min. Typ. Max. Units
Output Frequency 5pF load, Note 4 200 MHz
Output Clock Rise Time t
OR
0.66 to 2.64V 0.6 1.0 ns
Output Clock Fall Time t
OF
2.64 to 0.66V 0.6 1.0 ns
Propagation Delay 135 MHz, Note 1 1.5 2 4 ns
Buffer Additive Phase Jitter, RMS 125MHz, Integration range: 12kHz–20MHz 0.037 0.05 ps
Output to Output Skew Rising edges at VDD/2, Note 2 50 65 ps
Start-up Time t
START-UP
Part start-up time for valid outputs after VDD
ramp-up
2ms
Output Enable Time t
EN
CL < 5pF 3 cycles
Output Disable Time t
DIS
CL < 5pF 3 cycles
LOW SKEW 1 TO 4 CLOCK BUFFER 6 REVISION A 03/18/15
551S DATASHEET
Phase Noise Plots
The phase noise plots above show the low Additive Jitter of the 551S high-performance buffer. With an integration range of
12kHz to 20MHz, the reference input has about 62fs of RMS phase jitter while the output of 551S has about 77fs of RMS phase
jitter. This results in a low Additive Phase Jitter of only 45fs.
Test Load and Circuit
Figure 1. 551S Reference Phase Noise 62fs
(12kHz to 20MHz)
Figure 2. 551S Output Phase Noise 77fs
(12kHz to 20MHz)
Rs=33ohm
5
i
n
c
h
e
s
CL = 5pF
50ohms
P1-P3P4-P6P7-P9P10-P12

551SDCGI8

Mfr. #:
Buy 551SDCGI8
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1 to 4 50fs 50ps 200 MHz
Lifecycle:
New from this manufacturer.
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