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LTC3823IUH#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC3823
16
3823fd
INTV
CC
Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3823. The INTV
CC
pin can supply up to 50mA
RMS and must be bypassed to ground with a minimum
of 4.7μF low ESR tantalum capacitor or other low ESR
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate drivers.
Applications using large MOSFETs with a high input voltage
and high frequency of operation may cause the LTC3823
to exceed its maximum junction temperature rating or
RMS current rating. Most of the supply current drives the
MOSFET gates. In continuous mode operation, this current
is I
GATECHG
= f(Q
g(TOP)
+ Q
g(BOT)
). The junction temperature
can be estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the GN package is
limited to less than 23mA from a 30V supply:
T
J
= 70°C + (23mA)(30V)(80°C/W) = 125°C
For applications where more current is needed than INTV
CC
can supply, INTV
CC
can be driver by an external supply
with a voltage higher than 5.35V. However, the INTV
CC
pin
should not exceed its absolute maximum voltage of 7V.
External Gate Drive Buffers
The LTC3823 drivers are adequate for driving up to about
50nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating
at frequencies requiring greater RMS currents will benefi t
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 6
can be used.
Soft-Start and Tracking
The LTC3823 has the ability to either soft start by itself with
a capacitor or track the output of another supply. When
the device is confi gured to soft start by itself, a capacitor
should be connected to the TRACK/SS pin. The LTC3823
is put in a low quiescent current shutdown state (30μA)
if the RUN pin voltage is below 1.5V. The TRACK/SS
pin is actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.5V, the LTC3823 is
powered up. A soft-start current of 1.7μA then starts to
charge the soft-start capacitor C
SS
. Pin Z1/SS
ENABLE
must
be grounded for soft-start operation. Note that soft-start
is achieved not by limiting the maximum output current
of the controller but by controlling the ramp rate of the
output voltage. Current foldback is disabled during this
soft-start phase. During the soft-start phase, the LTC3823
is ramping the reference voltage until it is 20% below the
voltage set by the V
REFIN
pin. The forced continuous mode
is also disabled and PGOOD signal is forced low during this
phase. The total soft-start time can be calculated as:
t
SOFTSTART
= 0.5V • C
SS
/1.7μA
When the device is confi gured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TRACK/SS pin. Pin
Z1/SS
ENABLE
should be tied to INTV
CC
to turn off the soft-
start current in this mode. Therefore, the voltage ramp rate
on this pin is determined by the ramp rate of the other
supply output voltage.
Output Voltage Tracking
The LTC3823 allows the user to program how its output
ramps up and down by means of the TRACK/SS pin.
Through this pin, the output can be set up to either co-
incidentally or ratiometrically track with another supply’s
output, as shown in Figure 7. In the following discussions,
V
OUT1
refers to the master LTC3823’s output and V
OUT2
refers to the slave LTC3823’s output.
To implement the coincident tracking in Figure 7a, connect
an additional resistive divider to V
OUT1
and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio of
this divider should be selected the same as that of the slave
IC’s feedback divider shown in Figure 8. In this tracking
APPLICATIONS INFORMATION
Q1
FMMT619
GATE
OF M1
TG
BOOST
SW
Q2
FMMT720
Q3
FMMT619
GATE
OF M2
BG
3823 F06
INTV
CC
PGND
Q4
FMMT720
10Ω 10Ω
Figure 6. Optional External Gate Driver
LTC3823
17
3823fd
mode, V
OUT1
must be set higher than V
OUT2
. To implement
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC’s feedback divider. Note
that the pin Z1/SS
ENABLE
of the slave IC should be tied to
INTV
CC
so that the internal soft-start current is disabled
in both tracking modes or it will introduce a small error
on the tracking voltage depending on the absolute values
of the tracking resistive divider.
By selecting different resistors, the LTC3823 can achieve
different modes of tracking including the two in Figure 7.
So which mode should be programmed? While either
mode in Figure 7 satisfi es most practical applications,
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
help of Figure 9. At the input stage of the slave IC’s error
amplifi er, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.6V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current
and offer tight matching between V
FB2
and the internal
precision 0.6V reference. In the ratiometric mode, however,
TRACK/SS equals 0.6V at steady state. D1 will divert part
of the bias current to make V
FB2
slightly lower than 0.6V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a fi nite amount
of output voltage deviation. Furthermore, when the master
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
APPLICATIONS INFORMATION
TIME
(7a) Coincident Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
3823 F07
(7b) Ratiometric Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
Figure 7. Two Different Modes of Output Voltage Tracking
R3 R1
R4 R2
R3
V
OUT2
R4
(8a) Coincident Tracking Setup
TO
V
FB1
PIN
TO
TRACK/SS2
PIN
TO
V
FB2
PIN
V
OUT1
R1
R2
R3
V
OUT2
R4
3823 F08
(8b) Ratiometric Tracking Setup
TO
V
FB1
PIN
TO
TRACK/SS2
PIN
TO
V
FB2
PIN
V
OUT1
Figure 8. Setup for Coincident and Ratiometric Tracking
–
+
II
D1
TRACK/SS2
0.6V
V
FB2
D2
D3
3823 F09
EA2
Figure 9. Equivalent Input Current of Error Amplifi er
LTC3823
18
3823fd
Differential Amplifi er
This amplifi er provides true differential output voltage
sensing. Sensing both the positive and negative terminals
of the output voltage benefi ts regulation in high current
applications and/or applications having electrical intercon-
nection losses. Precision feedback resistors are integrated
in the IC with the amplifi er already confi gured as a unity-gain
differential amplifi er. It has a GBW product of 3.5MHz and
an open-loop gain of >120dB. The amplifi er can source
>2mA of current, and can be used in applications with
up to 3.3V output voltage. The amplifi er is not capable of
sinking signifi cant current, and must be resistively loaded.
A load of 20kΩ or less is recommended for stability. The
amplifi er is not designed to drive capacitive loads.
Phase-Locked Loop and Frequency Synchronization
The LTC3823 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency, f
O
. The center frequency is the operat-
ing frequency discussed in the previous section. The
LTC3823 incorporates a pulse detection circuit that will
detect a clock on the PLLIN pin. In turn, it will turn on the
phase-locked loop function. The pulse width of the clock
has to be greater than 400ns and the amplitude of the
clock should be greater than 2V.
During the start-up phase, phase-locked loop function is
disabled. When LTC3823 is not in synchronization mode,
PLLFLTR pin voltage is set to around 1.18V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLLFLTR
pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, Δf
H
,
is equal to the capture range, Δf
C
:
Δf
H
= Δf
C
= ±0.3 f
O
The output of the phase detector is a complementary pair of
current sources charging or discharging the external fi lter
network on the PLLFLTR pin. A simplifi ed block diagram
is shown in Figure 10.
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency f
O
, current is sourced continuously, pull-
ing up the PLLFLTR pin. When the external frequency is
less than f
O
, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor C
LP
holds the voltage. The LTC3823 PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin.
The loop fi lter components (C
LP
, R
LP
) smooth out the cur-
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The fi lter compo-
nents C
LP
and R
LP
determine how fast the loop acquires
lock. Typically R
LP
=10k and C
LP
is 0.01μF to 0.1μF.
Dead Time Control
To further optimize the effi ciency, the LTC3823 gives us-
ers some control over the dead time of the Top gate low
and Bottom gate high transition. By applying a DC voltage
on the Z0 pin, the TG low BG high dead time can be pro-
grammed. Because the dead time is a strong function of
APPLICATIONS INFORMATION
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PLLIN
PLLFLTR
2.4V
C
LP
3823 F10
R
LP
VCO
Figure 10. Phase-Locked Loop Block Diagram
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LTC3823IUH#TRPBF

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Buy LTC3823IUH#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Fast No Rsense Step-Down Synchronous Controller with Differential Output Sensing, Tracking and PLL
Lifecycle:
New from this manufacturer.
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