NLV14020BDR2G Datasheet MC14020BDG, NLV14020BDR2G | P4-P6

MC14020B

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4

SWITCHING CHARACTERISTICS (Note 5) (C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol

V

DD

Vdc

Min

Typ

(Note 6)

Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) C

L

+ 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) C

L

+ 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) C

L

+ 9.5 ns

t

TLH

,

t

THL

5.0

10

15

−

100

50

40

200

100

80

ns

Propagation Delay Time

Clock to Q1

t

PHL

, t

PLH

= (1.7 ns/pF) C

L

+ 175 ns

t

PHL

, t

PLH

= (0.66 ns/pF) C

L

+ 82 ns

t

PHL

, t

PLH

= (0.5 ns/pF) C

L

+ 55 ns

t

PLH

,

t

PHL

5.0

10

15

−

260

115

80

520

230

160

ns

Clock to Q14

t

PHL

, t

PLH

− (1.7 ns/pF) C

L

+ 1735 ns

t

PHL

, t

PLH

= (0.66 ns/pF) C

L

+ 772 ns

t

PHL

, t

PLH

= (0.5 ns/pF) C

L

+ 535 ns

5.0

10

15

−

1820

805

560

3900

1725

1200

ns

Propagation Delay Time

Reset to Q

n

t

PHL

= (1.7 ns/pF) C

L

+ 285 ns

t

PHL

= (0.66 ns/pF) C

L

+ 122 ns

t

PHL

= (0.5 ns/pF) C

L

+ 90 ns

t

PHL

5.0

10

15

−

370

155

115

740

310

230

ns

Clock Pulse Width t

WH

5.0

10

15

500

165

125

140

55

38

−

ns

Clock Pulse Frequency f

max

5.0

10

15

1.0

3.0

4.0

2.0

6.0

8.0

−

MHz

Clock Rise and Fall Time t

TLH

, t

THL

5.0

10

15

No Limit

−

Reset Pulse Width t

WL

5.0

10

15

3000

550

420

320

120

80

−

ns

Reset Recovery Time t

rec

5.0

10

15

−

65

25

15

130

50

30

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14020B

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5

Figure 1. Power Dissipation Test Circuit

and Waveform

Figure 2. Switching Time Test Circuit

and Waveforms

500 mF

0.01 mF

CERAMIC

PULSE

GENERATOR

V

DD

C

L

C

L

C

L

V

SS

C

R

Q1

Q4

Q

n

I

D

V

DD

V

SS

20 ns 20 ns

CLOCK

90%

50%

10%

50% DUTY CYCLE

PULSE

GENERATOR

V

DD

V

SS

C

R

Q1

Q4

Q

n

C

L

C

L

C

L

20 ns 20 ns

CLOCK

90%

50%

10%

t

WH

t

PLH

t

PHL

90%

50%

10%

t

TLH

t

THL

Q

Figure 3. Timing Diagram

CLOCK

RESET

Q1

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q14

16,384819240961 2 4 8 16 32 64 128 256 512 1024 2048

MC14020B

http://onsemi.com

6

PACKAGE DIMENSIONS

TSSOP−16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200

B 4.30 4.50 0.169 0.177

C −−− 1.20 −−− 0.047

D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.18 0.28 0.007 0.011

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH OR

GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER

SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER

SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT

DATUM PLANE -W-.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

7.06

16X

0.36

16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

NLV14020BDR2G

NLV14020BDR2G

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