ISL83699IRZ-T

10
FN6094.3
November 5, 2004
ISL83699
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA
E1
D
N
123
-B-
0.10(0.004) C AM BS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
α
0
o
8
o
0
o
8
o
-
Rev. 1 2/02
11
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6094.3
November 5, 2004
ISL83699
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
INDEX
D1/2
D1
D/2
D
E1/2 E/2
E
A
2X
0.15
B
C
0.10 BAMC
A
N
SEATING PLANE
N
6
3
2
2
3
e
1
1
0.08
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
CC
SECTION "C-C"
NX b
A1
C
2X
C
0.15
0.15
2X
B
0
REF.
(Nd-1)Xe
(Ne-1)Xe
REF.
5
A1
4X P
A
C
C
4X P
B
2X
AC0.15
A2
A3
D2
D2
E2
E2/2
TERMINAL TIP
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
C
L
C
L
e
e
E1
2
NX k
NX b
8
NX L
8
8
9
AREA
9
4X
0.10 C
/ /
9
(DATUM B)
(DATUM A)
AREA
INDEX
6
AREA
N
9
CORNER
OPTION 4X
L1
L
10
L1
L
10
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5, 8
D 3.00 BSC -
D1 2.75 BSC 9
D2 1.35 1.50 1.65 7, 8, 10
E 3.00 BSC -
E1 2.75 BSC 9
E2 1.35 1.50 1.65 7, 8, 10
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N162
Nd 4 3
Ne 4 3
P- -0.609
θ --129
Rev. 1 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2
and D2 MAX dimension.

ISL83699IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SWITC QD SPDTDL DPDT 0 3OHM S 1 65V TO 3
Lifecycle:
New from this manufacturer.
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