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ADUM3401TRWZ-EP-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Enhanced Product ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
Rev. 0 | Page 7 of 17
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
10 Mbps
V
DD1
Supply Current I
DD1 (10)
5 V/3.3 V Operation 6.0 7.5 mA 5 MHz logic signal frequency
3.3 V/5 V Operation 3.3 4.4 mA 5 MHz logic signal frequency
V
DD2
Supply Current
I
DD2 (10)
5 V/3.3 V Operation 3.3 4.4 mA 5 MHz logic signal frequency
3.3 V/5 V Operation 6.0 7.5 mA 5 MHz logic signal frequency
For All Models
Input Leakage per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
V
Ex
Input Pull-Up Current I
PU
−10 −3 V
Ex
= 0 V
Tristate Leakage Current per Channel I
OZ
−10 +0.01 +10 µA
Logic High Input Threshold
V
IH
, V
EH
5 V/3.3 V Operation 2.0 V
3.3 V/5 V Operation 1.6 V
Logic Low Input Threshold
V
IL
, V
EL
5 V/3.3 V Operation 0.8 V
3.3 V/5 V Operation 0.4 V
Logic High Output Voltages V
OAH
, V
OBH
(V
DD1
or V
DD2
)
−
0.1
(V
DD1
or V
DD2
) V I
Ox
2
= −20 µA, V
Ix
= V
IxH
3
V
OCH
, V
ODH
(V
DD1
or V
DD2
)
−
0.4
(V
DD1
or V
DD2
) −
0.2
V I
Ox
2
= −4 mA, V
Ix
= V
IxH
3
Logic Low Output Voltages
V
OAL
,
V
OBL
0.0
0.1
V
I
Ox
2
= 20 µA, V
Ix
= V
IxL
4
V
OCL
, V
ODL
0.04 0.1 V I
Ox
2
= 400 µA, V
Ix
= V
IxL
4
0.2 0.4 V I
Ox
2
= 4 mA, V
Ix
= V
IxL
4
SWITCHING SPECIFICATIONS
Minimum Pulse Width PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate 10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay t
PHL
, t
PLH
15 35 50 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew t
PSK
22 ns C
L
= 15 pF, CMOS signal levels
Channel to Channel Matching
Codirectional Channels t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Opposing Directional Channels t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Propagation Delay
Disable (High/Low-to-High Impedance) t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Enable (High Impedance-to-High/Low) t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
f
C
L
= 15 pF, CMOS signal levels
5 V/3.3 V Operation 3.0 ns
3.3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity
Logic High Output
5
|CM
H
| 25 35 kV/µs V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Logic Low Output
5
|CM
L
| 25 35 kV/µs V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate
f
r
5 V/3.3 V Operation 1.2 Mbps
3.3 V/5 V Operation 1.1 Mbps
ADuM3400-EP/ADuM3401-EP/ADuM3402-EP Enhanced Product
Rev. 0 | Page 8 of 17
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Dynamic Supply Current per Channel
6
I
DDI (D)
Input
5 V/3.3 V Operation 0.20 mA/Mbps
3.3 V/5 V Operation 0.10 mA/Mbps
Output
I
DDO (D)
5 V/3.3 V Operation 0.03 mA/Mbps
3.3 V/5 V Operation 0.05 mA/Mbps
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. See Figure 8 through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11
through Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM3400-EP/ADuM3401-EP/ADuM3402-EP channel configurations.
2
I
Ox
is the Channel x output current, where x = A, B, C, or D.
3
V
IxH
is the input side logic high.
4
V
IxL
is the input side logic low.
5
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
OUT
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The
transient magnitude is the range over which the common mode is slewed.
6
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions.
Enhanced Product ADuM3400-EP/ADuM3401-EP/ADuM3402-EP
Rev. 0 | Page 9 of 17
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)
1
R
IO
10
12
Ω
Capacitance (Input to Output)
1
C
IO
2.2 pF f = 1 MHz
Input Capacitance
2
C
I
4.0 pF
IC Junction to Case Thermal Resistance
Side 1 θ
JCI
33 °C/W Thermocouple located at center of package underside
Side 2 θ
JCO
28 °C/W Thermocouple located at center of package underside
1
Device considered a 2-terminal device; Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM3400-EP/ADuM3401-EP/ADuM3402-EP are pending approval by the organizations listed in Table 5.
Table 5.
UL (Pending) CSA (Pending) VDE (Pending)
Recognized under 1577 Component
Recognition Program
1
Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-12
2
Single Protection, 2500 V rms
Isolation Voltage
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM3400-EP/ADuM3401-EP/ADuM3402-EP is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current
leakage detection limit = 5 µA).
2
In accordance with DIN V VDE V 0884-10, each ADuM3400-EP/ADuM3401-EP/ADuM3402-EP is proof tested by applying an insulation test voltage ≥1050 V peak for
1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10
approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.8 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.8 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the
Printed Circuit Board (PCB Clearance)
L(PCB) 8.1 min mm Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADUM3401TRWZ-EP-RL

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Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators QUAD-CHANNEL DIGITAL ISOLATORS
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