MAX1182
Dual 10-Bit, 65Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
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Analog Inputs and Reference
Configurations
The full-scale range of the MAX1182 is determined by the
internally generated voltage difference between REFP
(V
DD
/ 2 + V
REFIN
/ 4) and REFN (V
DD
/ 2 - V
REFIN
/ 4).
The full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.
REFOUT, REFP, COM (V
DD
/ 2), and REFN are internal-
ly buffered low-impedance outputs.
The MAX1182 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes bypass REFIN with a > 10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN become outputs. REFOUT may be left open
or connected to REFIN through a > 10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high impedance and may
be driven through separate external reference sources.
Clock Input (CLK)
The MAX1182’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
SNR
dB
= 20
✕
log
10
(1 / [2π x f
IN
x t
AJ
]),
where f
IN
represents the analog input frequency and t
AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1182 clock input operates with a voltage thresh-
old set to V
DD
/ 2. Clock inputs with a duty cycle other
than 50%, must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1182
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (/OE)
All digital outputs, D0A–D9A (Channel A) and D0B–D9B
(Channel B), are TTL/CMOS logic-compatible. There is
a 5-clock-cycle latency between any particular sample
and its corresponding output data. The output coding
can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capaci-
tive load on the digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (< 15pF), to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1182, thereby degrading its
dynamic performance. Using buffers on the digital out-
puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1182 small-series
resistors (e.g., 100Ω) maybe added to the digital output
paths, close to the MAX1182.
Figure 4 displays the timing relationship between out-
put enable and data output valid as well as power
down/wake-up and data output valid.
Power-Down (PD) and
Sleep (SLEEP) Modes
The MAX1182 offers two power-save modes—sleep and
full power-down mode. In sleep mode (SLEEP = 1), only
the reference bias circuit is active (both ADCs are dis-
abled), and current consumption is reduced to 2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high impedance state.
