[AK5388]
MS1096-E-01 2009/08
- 22 -
Cascade TDM Mode
The AK5388 supports cascading of up to two devices in a daisy chain configuration in TDM256 mode. In this mode,
SDTO1 pin of device #1 is connected to TDMIN pin of device #2. The SDTO1 pin of device #2 can output 8-chnnels of
TDM data multiplexed with 4-chnnel of TDM data from device #1 and 4-channel of TDM data from device #2.
Figure 17
shows a connection example of a daisy chain.
When using two AK5388’s in slave mode by cascade connection, the internal timing between device #1 and #2 may differ
for 1MCLK clock cycle. BICK falling edge must me more than ±10ns from a MICK rising edge to prevent this phase
difference between two devices. (
Table 6)
BICK must be divided by two on a MCLK falling edge (
Figure 19) when MCLK=2 x BICK (Normal speed 512fs mode or
Double speed 256fs mode), and BICK must be in-phase signal to MCLK (
Figure 20) when MCLK = BICK (Normal
speed 256fs mode or Quad speed 128fs mode) to achieve this internal timing synchronization.
48kHz
256fs
8ch TDM
LRC
K
A
K5388 #1
BIC
K
TDMIN
SDTO1
SDTO2
MCL
K
256fs or 512fs
GND
LRC
K
A
K5388 #
2
BIC
K
TDMIN
SDTO1
SDTO2
MCL
K
Figure 17. Cascade TDM Connection Diagram
LRCK
BICK(256fs)
#1 SDTO1(o)
22 0
L1
32 BICK
256 BICK
22 0
R1
32 BICK
2223 23 2322 0
L2
32 BICK
22 0
R2
32 BICK
23 23
#1 SDTO2(o)
22 0
L1
32 BICK
22 0
R1
32 BICK
23 23 22 0
L2
32 BICK
22 0
R2
32 BICK
23 23
#2 TDMIN(i)
22 0
L1
32 BICK
22 0
R1
32 BICK
23 23 22 0
L2
32 BICK
22 0
R2
32 BICK
23 23
#2 SDTO1(o)
22 0
L1
32 BICK
22 0
R1
32 BICK
2223 23 2322 0
L2
32 BICK
22 0
R2
32 BICK
23 23 22 0
L1-#1
32 BICK
22 0
R1-#1
32 BICK
23 23 22 0
L2-#1
32 BICK
22 0
R2-#1
32 BICK
23 23
Figure 18. Cascade TDM Timing
[AK5388]
MS1096-E-01 2009/08
- 23 -
Parameter
Symbol min typ max Units
MCLK “” to BICK “
BICK “” to MCLK“
tMCB
tBIM
10
10
ns
ns
Table 6 TDM Mode Clock Timing
tBIM
VIH
tMCB
MCLK
VIL
VIH
BICK
VIL
Figure 19. Audio Interface timing (Slave mode, TDM0 Mode MCLK=2 x BICK)
tBIM
VIH
tMCB
MCLK
VIL
VIH
BICK
VIL
Figure 20. Audio Interface Timing (Slave mode, TDM0 Mode MCLK=BICK)
Mono mode
When the MONO pin is set to “H”, the AK5388 is in Mono mode. In this mode, dynamic range and S/N can be improved
by approximately 3dB when the same analog signal is inputted to LIN1 and RIN1, LIN2 and RIN2. The LIN1 and RIN1
data are summed and the amplitude is attenuated into half to be output from the SDTO1 pin. The LIN2 and RIN2 data are
summed and the amplitude is attenuated into half to be output from the SDTO2 pin.
MONO pin SDTO1/2 Output Data
L Stereo Mode
H Mono Mode
Table 7. Setup of MONO mode
[AK5388]
MS1096-E-01 2009/08
- 24 -
SYSTEM DESIGN
Figure 21 and Figure 22 show the system connection diagram. The evaluation board demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
LIN1+
VREFP1
1
LIN1-
44
2
VSS1 3
A
VDD14
TEST1
5
VSS2 6
CKS0 7
CKS1 8
CKS2
9
PDN 10
M_SN 11
VREFL1
43
VCOM1 42
RIN1+
41
RIN1
-
40
TEST3
39
LIN2
-
38
LIN2+
37
VCOM2
36
VREFL2 35
VREFP2
34
MCLK
12
BICK
13
LRCK
14
DVDD1
15
VSS3
16
SDTO1
17
SDTO2
18
OVF
19
TDMIN
20
TDM0
21
TDM1
22
33
32
31
30
29
28
27
26
25
24
23
RIN2+
RIN2-
VSS6
AVDD2
TEST2
VSS5
VSS4
DVDD2
HPFE
MONO
DIF
AK5388
Top View
+
Digital3.3
v
0.1u 10u
+
Analog5.0V
10u0.1u
0.1u
10u
+
0.1u
2.2u
+
10u 0.1u
0.1u
+
0.1u
+ +
Analog5.0V
+
0.1u
+
Digital3.3v
10u 2.2u
10u
Ceramic Capacitor
+
Electrolytic Capacitor
LIN1+
LIN1-
RIN2+
RIN2-
LIN2+
LIN2-
RIN1+
RIN1-
Micro-
Controller
fs
64fs
Micro-
Controller
A
nalog
Digital
Digital
Note:
- VSS1-6 should be distributed separately from the ground of external digital devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 21. Typical Connection Diagram

AK5388EQ

Mfr. #:
Manufacturer:
Description:
IC ADC AUDIO STER 24BIT 44LQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet