L4989D, L4989MD Application information
Doc ID 022376 Rev. 2 11/19
3 Application information
3.1 Voltage regulator
The voltage regulator uses a p-channel MOS transistor as a regulating element. With this
structure a very low dropout voltage at current up to 150 mA is obtained. The output voltage
is regulated up to transient input supply voltage of 40 V. No functional interruption due to
over-voltage pulses is generated.The voltage Regulator is always active and not depending
on the state of WE
n
input pin. A short circuit protection to GND is provided.
Figure 3. Behavior of output current versus regulated voltage V
o
3.2 Reset
The reset circuit supervises the output voltage V
o
. The V
o_th
reset threshold is defined with
the in-ternal reference voltage and a resistor output divider. If the output voltage becomes
lower than V
o_th
then Res goes low with a reaction time trr. The reset low signal is
guaranteed for an output voltage V
o
greater than 1 V.
When the output voltage becomes higher than V
o_th
then Res goes high with a delay t
rd
.
This delay is obtained by an internal oscillator.
The oscillator period is given by:
T
osc
= [(V
rhth
-V
rlth
) x C
tr
] / I
cr
+ [(V
rhth
-V
rlth
) x C
tr
] / I
dr
where:
I
cr
: is an internally generated charge current
I
dr
: is an internally generated discharge current
V
rhth
, V
rlth
: are two voltages defined with the output voltage and a resistor output
divider
C
tr
: is an external capacitance.
t
rd
is given by:
t
rd
= 512 x T
osc
The Reset is always active and not depending on the state of WE
n
input pin.
Vo
Vo_ref
IoutIshort Ilim
