IRFPS40N50L Datasheet IRFPS40N50LPBF, IRFPS40N50L | P4-P6

www.vishay.com Document Number: 91260

4 S11-0111-Rev. C, 07-Feb-11

IRFPS40N50L, SiHFPS40N50L

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Output Capacitance Stored Energy vs. V

DS

Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 8 - Typical Source Drain Diode Forward Voltage

1 10 100 1000

V

DS

, Drain-to-Source Voltage (V)

10

100

1000

10000

100000

1000000

C

,

C

a

p

a

c

i

t

a

n

c

e

(

p

F

)

Coss

Crss

Ciss

V

GS

= 0V, f = 1 MHZ

C

iss

= C

gs

+ C

gd

, C

ds

SHORTED

C

rss

= C

gd

C

oss

= C

ds

+ C

gd

0 100 200 300 400 500 600

V

DS,

Drain-to-Source Voltage (V)

0

5

10

15

20

25

30

35

40

E

n

e

r

g

y

(

µ

J

)

0 100 200 300 400

0

5

10

15

20

Q , Total Gate Charge (nC)

V , Gate-to-Source Voltage (V)

G

GS

I =

D

47A

V = 100V

DS

V = 250V

DS

V = 400V

DS

0.1

1

10

100

1000

0.2 0.7 1.2 1.7 2.2

V ,Source-to-Drain Voltage (V)

I , Reverse Drain Current (A)

SD

V = 0 V

GS

T = 25 C

J

°

T = 150 C

J

°

Document Number: 91260 www.vishay.com

S11-0111-Rev. C, 07-Feb-11 5

IRFPS40N50L, SiHFPS40N50L

Vishay Siliconix

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

25 50 75 100 125 150

0

10

20

30

40

50

T , Case Temperature ( C)

I , Drain Current (A)

°

C

D

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

0.001

0.01

0.1

1

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T =P x Z + T

1 2

J DM thJC C

P

t

DM

1

2

t , Rectangular Pulse Duration (sec)

Thermal Response

(Z )

1

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

www.vishay.com Document Number: 91260

6 S11-0111-Rev. C, 07-Feb-11

IRFPS40N50L, SiHFPS40N50L

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 12d - Maximum Safe Operating Area

Fig. 13a - Gate Charge Test Circuit

Fig. 13b - Basic Gate Charge Waveform

A

R

G

I

AS

0.01 Ω

t

p

D.U.T.

L

V

DS

+

-

V

DD

Driver

15 V

20 V

I

AS

V

DS

t

p

1

10

100

1000

10 100 100

OPERATION IN THIS AREA LIMITED

BY R

DS(on)

Single Pulse

T

= 150 C

= 25 C

°

J

C

V , Drain-to-Source Voltage (V)

I , Drain Current (A)I , Drain Current (A)

DS

D

10us

100us

1ms

10ms

25 50 75 100 125 150

0

500

1000

1500

2000

Starting T , Junction Temperature( C)

E , Single Pulse Avalanche Energy (mJ)

J

AS

°

I

D

TOP

BOTTOM

21A

30A

46A

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

IRFPS40N50L

IRFPS40N50L

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