AD843JRZ-16 Datasheet AD843JNZ, AD843KNZ, AD843JRZ-16 | P10-P12

AD843

REV. D

–9–

SAMPLE-AND-HOLD AMPLIFIER CIRCUITS

A Fast Switching Sample & Hold Circuit

A sample-and-hold circuit possessing short acquisition time and

low aperture delay can be built using an AD843 and discrete

JFET switches. The circuit of Figure 25 employs five n-channel

JFETs (with turn-on times of 35 ns) and an AD843 op amp

(which can settle to 0.01% in 135 ns). The circuit has an aper-

ture delay time of 50 ns and an acquisition time of 1 µs or less.

This circuit is based on a noninverting open loop architecture,

using a differential hold capacitor to reduce the effects of pedes-

tal error. The charge that is removed from CH1 by Q2 and Q3

is offset by the charge removed from CH2 by Q4 and Q5. This

circuit can tolerate low hold capacitor values (approximately

100 pF), which improve acquisition time, due to the small gate-

to-drain capacitance of the discrete JFETs. Although pedestal

error will vary with input signal level, making trimming more

difficult, the circuit has the advantages of high bandwidth and

short acquisition times. In addition, it will exhibit some

nonlinearity because both amplifiers are operating with a com-

mon-mode input. Amplifier A2, however, contributes less than

0.025% linearity error, due to its 72 dB common-mode rejec-

tion ratio.

To make sure the circuit accommodates a wide ±10 V input

range, the gates of the JFETs must be connected to a potential

near the –15 V supply. The level-shift circuitry (diode D3, PNP

transistor Q7, and NPN transistor Q6) shifts the TTL level S/H

command to provide for an adequate pinch-off voltage for the

JFET switches over the full input voltage range.

The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors

ensure signal acquisition for all conditions of V

and V

OUT

when the circuit switches from the sample to the hold mode.

Transistor Q1 provides an extra stage of isolation between the

output of amplifier A1 and the hold capacitor CH1.

When selecting capacitors for use in a sample-and-hold circuit,

the designer should choose those types with low dielectric

absorption and low temperature coefficients. Silvered-mica

capacitors exhibit low (0 to 100 ppm/°C) temperature coeffi-

cients and will still work in temperatures exceeding 200°C. It is

also recommend that the user test the chosen capacitor to insure

that its value closely matches that printed on it since not all

capacitors are fully tested by their manufacturers for absolute

tolerance.

A high speed CB amplifier, A1, follows the input signal. U1, a

dual wideband “T” switch, connects the input buffer amp to

one of the two output amplifiers while selecting the complemen-

tary amplifier to drive the A/D input. For example, when

“select” is at logic high, A1 drives CH1, A2 tracks the input sig-

nal and the output of A3 is connected to the input of the A/D

converter. At the same time, A3 holds an analog value and its

output is connected to the input of the A/D converter. When the

select command goes to logic LOW, the two output amplifiers

alternate functions.

Since the input to the A/D converter is the alternated “held”

outputs from A1 and A2, the offset voltage mismatch of the two

amplifiers will show up as nonlinearity and, therefore, distortion

in the output signal. To minimize this, potentiometers can be

used to adjust the offsets of the output amplifiers until they are

A PING-PONG S/H AMPLIFIER

For improved throughput over the circuit of Figure 25, a “ping-

pong” architecture may be used. A ping-pong circuit overcomes

some of the problems associated with high speed S/H amplifiers

by allowing the use of a larger hold capacitor for a given sample

rate: this will reduce the associated feedthrough, droop and ped-

estal errors.

Figure 26 illustrates a simple, four-chip ping-pong sample-and-

hold amplifier circuit. This design increases throughput by using

one channel to acquire a new sample while another channel

holds the previous sample. Instead of having to reacquire the

signal when switching from hold to sample mode, it alternately

connects the outputs from Channel 1 or from Channel 2 to the

A/D converter. In this case, the throughput is the slew rate and

settling time of the output amplifiers, A2 and A3.

Figure 25. A Fast Switching Sample-and-Hold Amplifier

REV. D

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AD843

equal. Alternatively, an autocalibration circuit using two D/A

converters can be employed. This can also be used to calibrate

out the effects of offset voltage drift over temperature.

The switch choice, for U1s, is critical in this type of design. The

DG542 utilizes “T” switching techniques on each channel for

exceptionally low crosstalk and for high isolation. The part fur-

ther improves these specifications by using ground pins between

the signal pins. With an input frequency of 5 MHz, crosstalk

and isolation are –85 dB and –75 dB, respectively. A limitation

of this switch is that it operates from a maximum –5 V negative

supply, making bipolar operation more difficult. It is recom-

mended that amplifiers A1, A2 and A3 operate from the same

–5 V supply to minimize any potential latch-up problems.

Figure 26. A Ping-Pong Sample-and-Hold Amplifier

Figure 27. Settling Time Test Circuit

AD843

REV. D

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MEASURING AD843 SETTLING TIME

Figure 28 shows the dynamic response of the AD843 while op-

erating in the settling time test circuit of Figure 27. The input of

the settling time fixture is driven by a flat-top pulse generator.

The error signal output from A1, the AD843 under test, is am-

plified by op amp A2 and then clamped by two high speed

Schottky diodes.

Figure 28. Settling Characteristics: +10 V to 0 V Step.

Upper Trace: Amplified Error Voltage (0.01%/Div)

Lower Trace: Output of AD843 Under Test (5 V/Div)

The error signal is clamped to prevent it from greatly overload-

ing the oscilloscope preamp. A Tektronix oscilloscope preamp

type 7A26 was chosen because it will recover from the approxi-

mately 0.4 volt overload, quickly enough to allow accurate mea-

surement of the AD843’s 135 ns settling time. Amplifier A2 is a

very high speed op amp; it provides a voltage gain of 10, provid-

ing a total gain of 5 from the error signal to the oscilloscope input.

A FAST PEAK DETECTOR CIRCUIT

The peak detector circuit of Figure 29, can accurately capture

the amplitude of input pulses as narrow as 200 ns and can hold

their value with a droop rate of less than 20 µV/µs. This circuit

will capture the peak value of positive polarity waveforms; to

detect negative peaks, simply reverse the polarity of the two

diodes.

The high bandwidth and 200 V/µs slew rate of amplifier A2, an

AD843, allows the detector’s output to “keep up” with its input

thus minimizing overshoot. The low (<1 nA) input current of

the AD843 ensures that the droop rate is limited only by the

reverse leakage of diode D2, which is typically <10 nA for the

type shown. The low droop rate is apparent in Figure 30. The

detector’s output (top trace) loses slightly over a volt of the

8 volt peak input value (bottom trace) in 75 ms, or a rate of

approximately 16 µV/µs.

Figure 30. Peak Detector Response to 125 Hz Pulse Train

Figure 31. Peak Capture Time

Amplifier A1, an AD847, can drive 680 pF hold capacitor, C

fast enough to “catch-up” with the next peak in 100 ns and still

settle to the new value in 250 ns, as illustrated in Figure 31.

Reducing the value of capacitor C

to 100 pF will maximize the

speed of this circuit at the expense of increased overshoot and

droop. Since the AD847 can drive an arbitrarily large value of

capacitance, C

can be increased to reduce droop, at the expense

of response time.

Figure 29. A Fast Peak Detector Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD843JRZ-16

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Description:

High Speed Operational Amplifiers 34MHz CBFET Fast Settling

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AD843JRZ-16

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