Nexperia
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 9 March 2017
13 / 23
11.1 Waveforms and test circuit
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t
h
t
su
t
h
t
PHL
t
W
t
PLH
t
su
1/f
max
V
M
V
M
V
M
V
I
GND
V
I
GND
CP input
D input
V
OH
V
OL
Q output
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP
to D hold times and the maximum input clock frequency
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MR input
CP input
Q output
t
PHL
t
W
t
rec
V
M
V
I
GND
V
I
V
OH
V
OL
GND
V
M
V
M
Measurement points are given in Table 9.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 8. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width and the MR to
CP recovery time
Table 9. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V 0.5 × V
CC
0.5 × V
CC
V
CC
≤ 3.0 ns
