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ICS8442AYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
8442AYI www.idt.com REV. D JULY 16, 2010
7
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Cycle-to-Cycle Jitter
Period Jitter
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Histogram
OUTPUT RISE/FALL TIME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SWING
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
nFOUT0, nFOUT1
FOUT0, FOUT1
➤
➤
➤
➤
nFOUT0,
nFOUT1
FOUT0,
FOUT1
t
sk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
3.3V OUTPUT LOAD TEST CIRCUIT
out
out
LVDS
DC Input
➤
➤
➤
V
OS
/Δ V
OS
V
DD
➤
➤
➤
100
out
out
LVDS
DC Input
V
OD
/Δ V
OD
V
DD
SCOPE
Qx
nQx
LVDS
Power Supply
+
-
Float GND
t
cycle n
t
cycle n+1
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
8442AYI www.idt.com REV. D JULY 16, 2010
8
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common fre-
Table 8. Common SANs Application Frequencies
Table 9. Configuration Details for SANs Applications
APPLICATION INFORMATION
ygolonhceTtcennocretnIetaRkcolC
SEDRESotycneuqerFecnerefeR
)zHM(
ycneuqerFlatsyrC
)zHM(
tenrehtEtibagiGzHG52
.152.651,052,52152135.91,52
lennahCerbiF
zHG5260.11CF
zHG0521.22CF
5218.231,521.35,52.60152,5265106.61
dnabin
ifnIzHG5.2052,52152
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8442I provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. V
DD
and V
DDA
, should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply
isolation is required.
Figure 2
illustrates how a 10Ω along
|with a 10μF and a .01μF bypass capacitor should be
connected to each V
DDA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DD
tcennocretnI
ygolonhceT
ycneuqerFlatsyrC
)zHM(
I2448SCI
ycneuqerFtuptuO
SEDRESot
)zHM(
I2448SCI
sgnitteSN&M
8M7M6
M5M4M3M2M1M0M1N0N
tenrehtEtibagiG
52521 00001010010
52052 00001010001
5252.651 00001100110
52135.9152.651 00010000010
1lennahCrebiF
52521.35 00001000111
5252.601 00001000110
2lennahCrebiF5265106.615
218.231 00010000010
dnabinifnI
52521 00001010010
52052 00001010001
quencies used as well as the settings for the ICS8442I to gen-
erate the appropriate frequency.
8442AYI www.idt.com REV. D JULY 16, 2010
9
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS8442I has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
Figure 3. CRYSTAL INPUt INTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3
. Typical results using parallel 18pF crystals are shown
in Table 10.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100Ω differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
100
ΩΩ
ΩΩ
Ω Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
DIFFERENTIAL DUTY CYCLE IMPROVEMENT
The schematic below is recommended for applications using the
÷1 output configuration for improving the differential duty cycle.
FIGURE 5. DIFFERENTIAL DUTY CYCLE IMPROVEMENT
3.3V
3.3V
LVDS_DRIVER
R1
100
HiPerClockS
Zo = 50 Ohm
Zo = 50 Ohm
nCLK
CLK
R1
100
C1
.1uf
Vcc = 3.3V
R3
800
LVDS Driv er
R2
1.3k
Zo = 50
R4
1.3k
C2
.1uf
Receiv er_dif
+
-
Zo = 50
R5
800
C1
18p
X1
18pF Parallel Crystal
C2
22p
XTAL_IN
XTAL_OUT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ICS8442AYILFT

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IC SYNTHESIZE DUAL 700MHZ 32LQFP
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