MC10H175M

Semiconductor Components Industries, LLC, 2006
February, 2006 Rev. 7
1 Publication Order Number:
MC10H175/D
MC10H175
Quint Latch
Description
The MC10H175 is a quint D type latch with common reset and
clock lines. This MECL 10KH part is a functional/pinout duplication
of the standard MECL 10K family part, with 100% improvement in
propagation delay and no increase in powersupply current.
Features
Propagation Delay, 1.2 ns Typical
Power Dissipation, 400 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K Compatible
PbFree Packages are Available*
TRUTH TABLE
DIP
PIN ASSIGNMENT
V
CC1
Q2
Q3
Q4
D4
C0
C1
V
EE
V
CC2
Q1
Q0
D2
D1
RESET
D0
D3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DC0C1 Reset Q
n+1
L
H
X
X
X
X
L
L
H
X
H
X
L
L
X
H
X
H
X
X
L
L
H
H
L
H
Qn
Qn
L
L
Pin assignment is for DualinLine Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
CDIP16
L SUFFIX
CASE 620A
MARKING DIAGRAMS*
PDIP16
P SUFFIX
CASE 648
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
SOEIAJ16
CASE 966
16
1
16
1
MC10H175P
AWLYYWWG
1
16
MC10H175L
AWLYYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G= PbFree Package
10H175
ALYWG
PLLC20
FN SUFFIX
CASE 775
20
1
10H175G
AWLYYWW
120
MC10H175
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2
Table 1. MAXIMUM RATINGS
Symbol Characteristic Rating Unit
V
EE
Power Supply (V
CC
= 0) 8.0 to 0 Vdc
V
I
Input Voltage (V
CC
= 0) 0 to V
EE
Vdc
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range 0 to +75 °C
T
stg
Storage Temperature Range Plastic
Ceramic
55 to +150
55 to +165
°C
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 2. ELECTRICAL CHARACTERISTICS (V
EE
= 5.2 V ±5%) (Note 1)
0° 25° 75°
Symbol Characteristic Min Max Min Max Min Max Unit
I
E
Power Supply Current 107 97 107 mA
I
inH
Input Current High
Pins 5,6,7,9,10,12,13
Pin 11
565
1120
335
660
335
660
mA
I
inL
Input Current Low 0.5 0.5 0.3
mA
V
OH
High Output Voltage 1.02 0.84 0.98 0.81 0.92 0.735 Vdc
V
OL
Low Output Voltage 1.95 1.63 1.95 1.63 1.95 1.60 Vdc
V
IH
High Input Voltage 1.17 0.84 1.13 0.81 1.07 0.735 Vdc
V
IL
Low Input Voltage 1.95 1.48 1.95 1.48 1.95 1.45 Vdc
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is
maintained. Outputs are terminated through a 50 W resistor to 2.0 V.
Table 3. AC PARAMETERS
0° 25° 75°
Symbol Characteristic Min Max Min Max Min Max Unit
t
pd
Propagation Delay
Data
Clock
Reset
0.6
0.7
1.0
1.6
1.9
2.2
0.6
0.7
1.0
1.6
2.0
2.3
0.6
0.8
1.0
1.7
2.1
2.4
ns
t
set
Setup Time 1.5 1.5 1.5 ns
t
hold
Hold Time 0.8 0.8 0.8 ns
t
r
Rise Time 0.5 1.8 0.5 1.9 0.5 2.0 ns
t
f
Fall Time 0.5 1.8 0.5 1.9 0.5 2.0 ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
MC10H175
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3
APPLICATION INFORMATION
The MC10H175 is a high speed, low power quint latch. It
features five D type latches with common reset and a
common twoinput clock. Data is transferred on the
negative edge of the clock and latched on the positive edge.
The two clock inputs are “OR”ed together.
Any change on the data input will be reflected at the
outputs while the clock is low. The outputs are latched on the
positive transition of the clock. While the clock is in the high
state, a change in the information present at the data inputs
will not affect the output information. THE RESET INPUT
IS ENABLED ONLY WHEN THE CLOCK IS IN THE
HIGH STATE.
D0 10 14 Q0D
C
Q
R
C0 6
C1 7
RESET 11
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
D
C
Q
R
D
C
Q
R
D
C
Q
D
C
Q
R
D
C
Q
R
15 Q1
2 Q2
3 Q3
4 Q4
D1 12
D2 13
D3 9
D4 5

MC10H175M

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Latches ECL Quint Latch
Lifecycle:
New from this manufacturer.
Delivery:
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