6.42
6
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
IDT70V3599/89S
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/W
Byte 3
I/O
27-35
Byte 2
I/O
18-26
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X
↑
HXXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X
↑
XLXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X
↑
L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected
X
↑
L H H H H L L High-Z High-Z High-Z D
IN
Write to Byte 0 Only
X
↑
LHHHLHLHigh-ZHigh-Z D
IN
High-Z Write to Byte 1 Only
X
↑
LHHLHHLHigh-Z D
IN
High-Z High-Z Write to Byte 2 Only
X
↑
LHLHHHL D
IN
High-Z High-Z High-Z Write to Byte 3 Only
X
↑
L H H H L L L High-Z High-Z D
IN
D
IN
Write to Lower 2 Bytes Only
X
↑
LHLLHHL D
IN
D
IN
High-Z High-Z Write to Upper 2 bytes Only
X
↑
LHLLLLL D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L
↑
L H H H H L H High-Z High-Z High-Z D
OUT
Read Byte 0 Only
L
↑
LHHHLHHHigh-ZHigh-ZD
OUT
High-Z Read Byte 1 Only
L
↑
LHHLHHHHigh-ZD
OUT
High-Z High-Z Read Byte 2 Only
L
↑
LHLHHHHD
OUT
High-Z High-Z High-Z Read Byte 3 Only
L
↑
LHHHLLHHigh-ZHigh-ZD
OUT
D
OUT
Read Lower 2 Bytes Only
L
↑
LHLLHHHD
OUT
D
OUT
High-Z High-Z Read Upper 2 Bytes Only
L
↑
LHLLLLHD
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H
↑
LHLLLLXHigh-ZHigh-ZHigh-ZHigh-ZOutputs Disabled
5617 tbl 02
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
0, CE1 and BEn
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
External
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS CNTEN REPEAT
(6 )
I/O
(3 )
MODE
XXAn
↑
XX L
(4 )
D
I/O
(0) Counter Reset to last valid ADS load
An X An
↑
L
(4 )
XHD
I/O
(n) External Address Used
An Ap Ap
↑
HH H D
I/O
(p) External Address Blocked—Counter disabled (Ap reused)
XApAp + 1
↑
H L
(5 )
HD
I/ O
(p+1) Counter Enabled—Internal Address generation
5617 tbl 03