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ESD7461N2T5G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. P0
1 Publication Order Number:
ESD7102/D
ESD7102, SZESD7102
Product Preview
ESD Protection Diodes
Low Capacitance ESD Protection Diodes
for High Speed Data Line
The ESD7102 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The small form factor,
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as USB 3.0 and HDMI.
Features
• Low Capacitance (0.3 pF Typical, I/O to GND)
• Short to Battery Survivability
• Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD)
• Low ESD Clamping Voltage (30 V Typical, +16 A TLP, I/O to GND)
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• USB2.0/3.0
• LVDS
• HDMI
• High Speed Differential Pairs
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Operating Junction Temperature Range T
J
−55 to +125 °C
Storage Temperature Range T
stg
−55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
260 °C
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ESD ±8
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
MARKING
DIAGRAM
SC−75
CASE 463
PIN CONFIGURATION
AND SCHEMATIC
www.
onsemi.com
Pin 1 Pin 2
Pin 3
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
=
1
2
3
XX M
XX = Specific Device Code
M = Date Code
1
ESD7102, SZESD7102
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Parameter
Symbol Conditions Min Typ Max Unit
Reverse Working
Voltage
V
RWM
I/O Pin to GND 5 16 V
Breakdown Voltage V
BR
I
T
= 1 mA, I/O Pin to GND 16.5 V
Reverse Leakage
Current
I
R
V
RWM
= 5 V, I/O Pin to GND 1
mA
Clamping Voltage
(Note 1)
V
C
IEC61000−4−2, ±8 kV Contact See Figures 3 and 4
Clamping Voltage TLP
(Note 2)
V
C
I
PP
= 8 A
I
PP
= 16 A
I
PP
= −8 A
I
PP
= −16 A
25
30
−5.5
−10.8
V
Junction Capacitance
Match
DC
J
VR = 0 V, f = 1 MHz between I/O1 to GND and I/O
2 to GND
5 10 %
Junction Capacitance C
J
VR = 0 V, f = 1 MHz between I/O Pins 0.2 0.4 pF
Junction Capacitance C
J
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.5 pF
3dB Bandwidth f
BW
R
L
= 50 W
5 GHz
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50 W, t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
1.0
Figure 1. Typical IV Characteristic Curve Figure 2. Typical CV Characteristic Curve
0
1E−02
VOLTAGE (V) VBias (V)
CURRENT (A)
CAPACITANCE (pF)
2
1E−03
1E−04
1E−05
1E−06
1E−07
1E−08
1E−09
1E−10
1E−11
1E−12
1E−13
468101214 2422201816
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
−50
150
TIME (ns)
VOLTAGE (V)
0
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
−10
50 100 150 200 400250 300 350
Figure 4. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
−20
10
TIME (ns)
VOLTAGE (V)
0 20 40 80 120 20
0
140 160 180
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
10060
02468101214
TBD TBD
ESD7102, SZESD7102
www.onsemi.com
3
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
Figure 6. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
P1-P3P4-P6

ESD7461N2T5G

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Buy ESD7461N2T5G
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors 16V ESD PROTECTION
Lifecycle:
New from this manufacturer.
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