NCV4279B
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7
APPLICATION NOTES
FLAG MONITOR
Figure 14 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 13. As the output voltage
falls (V
OUT
), the Monitor threshold is crossed. This causes
the voltage on the FLAG
output to go low sending a warning
signal to the microprocessor that a RESET
signal may occur
in a short period of time. T
WA RN I NG
is the time the
microprocessor has to complete the function it is currently
working on and get ready for the RESET
shutdown signal.
Figure 14. FLAG Monitor Circuit Waveform
OUT
MON
RESET
LAG Monitor
Ref. Voltage
T
WARNING
FLAG
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
t
DELAY
+
[
C
DELAY
(V
dt
* Reset Delay Low Voltage)
]
Delay Charge Current
Example:
Using C
DELAY
= 33 nF.
Assume reset Delay Low Voltage = 0.
Use the typical value for V
dt
= 1.8 V.
Use the typical value for Delay Charge Current = 2.5 mA.
t
DELAY
+
[
33 nF(1.8 * 0)
]
2.5 mA
+ 23.8 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C
OUT
shown in Figure 15
should work for most applications, however it is not
necessarily the optimized solution.
Figure 15. Test and Application Circuit Showing
Output Compensation
IN
V
OUT
C
OUT
**
10 mF
R
RST
RESET
C
IN
*
0.1 mF
NCV4279B
C
IN
required if regulator is located far from the power supply filte
**C
OUT
required for stability. Capacitor must operate at minimum
temperature expected.
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 16) is:
D(max)
+ [V
IN(max)
* V
OUT(min)
]I
OUT(max)
(
) V
IN(max)
I
Q
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the
application, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
qJA
+
150°C *
T
A
P
D
(2)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR®
I
Q
Control
Features
I
OUT
I
IN
Figure 16. Single Output Regulator with Key
Performance Parameters Labeled
V
IN
V
OUT
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